sram.c

基于东南大学开发的SEP3203的ARM7中的所有驱动

#include "hardware.h"
#include "hardware_reg.h"
#include "HA_typedef.h"

extern U32 para;


void HA_INIT_SRAM(void)
{
	U32 temp;
	
	/* read results and compare with the original */
	temp = *(RP)EMIADDR_SMCONF;
	para = HA_EMI_WRIT(para, temp);
	
}


U32 Dma_SRAM_Write(U32 SRAM_Add, U32 Dma_src_Add, U32 size, U32 channelnum)                  //just burst size = 4;
{        
	U32 	i,j,temp;						
	U32 	tempsrc,tempdest,tempcontrol,tempconfig;		//These 4 temp regiser address rariable are used to replase registers
															//    of registers of channel which is used now 
	tempsrc = DMACbase + 0x1000 + channelnum * 0x100;					//replase registers of channel to be used;
	tempdest = DMACbase + 0x1004 + channelnum * 0x100;
	tempcontrol = DMACbase + 0x100c + channelnum * 0x100;
	tempconfig = DMACbase + 0x1010 + channelnum * 0x100;
                                                           //size:num of word,should be muiltpy of 16(words)
  	*(RP)tempsrc = Dma_src_Add;   
	*(RP)tempdest = SRAM_Add;
	
	i = (U32)(size << 14);
	j=i+0x349B;       /* 0x349b=0`b0011 010 010 011 011 */          
	*(RP)tempcontrol = j;
	*(RP)tempconfig =0x0019;						//channel enable!
	
	/* check the transfer complete or not */
	#if 1
	do{ 
		temp = *(RP)tempconfig;
		temp &= 0x01;
	}while(temp != 0x0);
	#endif
	
	
	return 0;
    
}


U32 Dma_SRAM_Read(U32 SRAM_Add, U32 Dma_des_Add, U32 size, U32 channelnum)                  	//just burst size = 4;
{                                                                               			//size:num of word,should be muiltpy of 16(words)
 	U32 	i,j,temp;						
	U32 	tempsrc,tempdest,tempcontrol,tempconfig;		//These 4 temp regiser address rariable are used to replase registers
									//    of registers of channel which is used now 
	tempsrc = DMACbase + 0x1000 + channelnum * 0x100;			//replase registers of channel to be used;
	tempdest = DMACbase + 0x1004 + channelnum * 0x100;
	tempcontrol = DMACbase + 0x100c + channelnum * 0x100;
	tempconfig = DMACbase + 0x1010 + channelnum * 0x100;
	                                             		//size:num of word,should be muiltpy of 16(words)
   	*(RP)tempsrc = SRAM_Add; 
	*(RP)tempdest = Dma_des_Add ;
	
	i = (U32)(size << 14);
	j=i+0x349B;                                                         //suradd and desadd not add up
	*(RP)tempcontrol = j;
	*(RP)tempconfig =0x0019;						//channel enable!
	
	/* check the transfer complete or not */
	do{ 
		temp = *(RP)tempconfig;
		temp &= 0x01;
	}while(temp != 0x0);
	
   return 0;
}


static U32	sram32 = 0x24004800;
static U32	sram16 = 0x24004c00;
static U32	sram8 = 0x24004e00;

void SRAM_Read(U32 src, U32 size, U32 bit)
{
	U32 temp32;
	U16 temp16;
	U8  temp8;
	switch(bit){
	U32 i;
	case 8:
		for(i = 0; i < size; i++, temp8++) *(U8 *)(sram8 + i) = *(U8 *)(src + i);
		break;
	case 16:
	 	for(i = 0; i < size; i++, temp16++) *(U16 *)(sram16 + i * 2)= *(U16 *)(src + i * 2);
		break;
	case 32:
		for(i = 0; i < size; i++, temp32++) *(U32 *)(sram32 + i * 4) = *(U32 *)(src + i * 4);
		break;
	}
}    


void SRAM_Write(U32 dest, U32 size, U32 bit)
{
	U32 temp32 = 0;
	U16 temp16 = 0;
	U8 temp8 = 0;
	switch(bit){
	U32 i;
	case 8:
		for(i = 0; i < size; i++, temp8++) *(U8 *)(dest + i) = temp8;
		break;
	case 16:
	 	for(i = 0; i < size; i++, temp16++) *(U16 *)(dest + i * 2)= temp16;
		break;
	case 32:
		for(i = 0; i < size; i++, temp32++) *(U32 *)(dest + i * 4) = temp32;
		break;
	}
    
}

static void SRAM_FullWrite(U32 dest, U32 size, U32 bit)
{
	U32 i;
	for(i = 0; i < size; i++) *(U8 *)(dest + i) = 0x5a;
}

void SRAM(void)
{
	//HA_INIT_SRAM();
	SRAM_Write(0x24010000, 0x100, 32);
	SRAM_Read(0x24010000, 0x100, 32);
	compare(0x24004800, 0x24010000, 0x100, 32);
	
	SRAM_Write(0x24020000, 0x100, 16);
	SRAM_Read(0x24020000, 0x100, 16);
	compare(0x24004c00, 0x24020000, 0x100, 16);
	
	SRAM_Write(0x24030000, 0x100, 8);
	SRAM_Read(0x24030000, 0x100, 8);
	compare(0x24004e00, 0x24030000, 0x100, 8);
	
	//SRAM_FullWrite(0x24000000, 0x100000, 8);
	
	/* sram不稳定，常出错误*/
	//Dma_SRAM_Write(0x20001000, 0x1fff3800, 0x100, 0);
	//Dma_SRAM_Write(0x24002000, 0x1fff3800, 0x100, 1);
	//Dma_SRAM_Write(0x24003000, 0x1fff3800, 0x100, 2);
	//Dma_SRAM_Write(0x24004000, 0x1fff3800, 0x100, 3);
	//Dma_SRAM_Write(0x24005000, 0x1fff3800, 0x100, 4);
	//Dma_SRAM_Write(0x24006000, 0x1fff3800, 0x100, 5); 
	                
	//Dma_SRAM_Read(0x20001000, 0x1fff4c00, 0x100, 3);                  	//just burst size = 4;

}