📄 alpha.md
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stmt: ASGNI2(addr,reg) "stw $%1,%0\n" 1
stmt: ASGNU2(addr,reg) "stw $%1,%0\n" 1
stmt: ASGNI4(addr,reg) "stl $%1,%0\n" 1
stmt: ASGNU4(addr,reg) "stl $%1,%0\n" 1
stmt: ASGNI8(addr,reg) "stq $%1,%0\n" 1
stmt: ASGNU8(addr,reg) "stq $%1,%0\n" 1
stmt: ASGNP8(addr,reg) "stq $%1,%0\n" 1
reg: INDIRI1(reg) "ldb $%c,($%0)\n" 1
reg: INDIRI2(reg) "ldw $%c,($%0)\n" 1
reg: INDIRI4(addr) "ldl $%c,%0\n" 1
reg: INDIRI8(addr) "ldq $%c,%0\n" 1
reg: INDIRP8(addr) "ldq $%c,%0\n" 1
reg: INDIRU1(reg) "ldbu $%c,($%0)\n" 1
reg: INDIRU2(reg) "ldwu $%c,($%0)\n" 1
reg: INDIRU4(addr) "ldl $%c,%0\nzap $%c,240,$%c\n" 2
reg: INDIRU8(addr) "ldq $%c,%0\n" 1
reg: CVII4(INDIRI1(reg)) "ldb $%c,($%0)\n" 1
reg: CVII8(INDIRI1(reg)) "ldb $%c,($%0)\n" 1
reg: CVII4(INDIRI2(reg)) "ldw $%c,($%0)\n" 1
reg: CVII8(INDIRI2(reg)) "ldw $%c,($%0)\n" 1
reg: CVII8(INDIRI4(addr)) "ldl $%c,%0\n" 1
reg: CVUU4(INDIRU1(reg)) "ldbu $%c,($%0)\n" 1
reg: CVUU8(INDIRU1(reg)) "ldbu $%c,($%0)\n" 1
reg: CVUU4(INDIRU2(reg)) "ldwu $%c,($%0)\n" 1
reg: CVUU8(INDIRU2(reg)) "ldwu $%c,($%0)\n" 1
reg: CVUU8(INDIRU4(addr)) "ldl $%c,%0\nzap $%c,240,$%c\n" 2
reg: CVUI4(INDIRU1(reg)) "ldbu $%c,($%0)\n" 1
reg: CVUI8(INDIRU1(reg)) "ldbu $%c,($%0)\n" 1
reg: CVUI4(INDIRU2(reg)) "ldwu $%c,($%0)\n" 1
reg: CVUI8(INDIRU2(reg)) "ldwu $%c,($%0)\n" 1
reg: CVUI8(INDIRU4(addr)) "ldl $%c,%0\nzap $%c,240,$%c\n" 2
reg: CVIU8(reg) "mov $%0,$%c\n" move(a)
reg: INDIRF4(addr) "lds $f%c,%0\n" 1
reg: INDIRF8(addr) "ldt $f%c,%0\n" 1
stmt: ASGNF4(addr,reg) "sts $f%1,%0\n" 1
stmt: ASGNF8(addr,reg) "stt $f%1,%0\n" 1
reg: MULI4(reg,rc) "mull $%0,%1,$%c\n" 1
reg: MULI8(reg,rc) "mulq $%0,%1,$%c\n" 1
reg: MULU4(reg,rc) "mull $%0,%1,$%c\nzap $%c,240,$%c\n" 2
reg: MULU8(reg,rc) "mulq $%0,%1,$%c\n" 1
reg: DIVI4(reg,rc) "divl $%0,%1,$%c\n" 1
reg: DIVI8(reg,rc) "divq $%0,%1,$%c\n" 1
reg: DIVU4(reg,rc) "divlu $%0,%1,$%c\n" 1
reg: DIVU8(reg,rc) "divqu $%0,%1,$%c\n" 1
reg: MODI4(reg,rc) "reml $%0,%1,$%c\n" 1
reg: MODI8(reg,rc) "remq $%0,%1,$%c\n" 1
reg: MODU4(reg,rc) "remlu $%0,%1,$%c\n" 1
reg: MODU8(reg,rc) "remqu $%0,%1,$%c\n" 1
rc: con "%0"
rc: reg "$%0"
reg: ADDI4(reg,rc) "addl $%0,%1,$%c\n" 1
reg: ADDI8(reg,rc) "addq $%0,%1,$%c\n" 1
reg: ADDP8(reg,rc) "addq $%0,%1,$%c\n" 1
reg: ADDU4(reg,rc) "addl $%0,%1,$%c\nzap $%c,240,$%c\n" 2
reg: ADDU8(reg,rc) "addq $%0,%1,$%c\n" 1
reg: SUBI4(reg,rc) "subl $%0,%1,$%c\n" 1
reg: SUBI8(reg,rc) "subq $%0,%1,$%c\n" 1
reg: SUBP8(reg,rc) "subq $%0,%1,$%c\n" 1
reg: SUBU4(reg,rc) "subl $%0,%1,$%c\nzap $%c,240,$%c\n" 2
reg: SUBU8(reg,rc) "subq $%0,%1,$%c\n" 1
reg: BANDI4(reg,rc) "and $%0,%1,$%c\naddl $%c,0,$%c\n" 2
reg: BANDI8(reg,rc) "and $%0,%1,$%c\n" 1
reg: BANDU4(reg,rc) "and $%0,%1,$%c\n" 1
reg: BANDU8(reg,rc) "and $%0,%1,$%c\n" 1
reg: BORI4(reg,rc) "or $%0,%1,$%c\naddl $%c,0,$%c\n" 2
reg: BORI8(reg,rc) "or $%0,%1,$%c\n" 1
reg: BORU4(reg,rc) "or $%0,%1,$%c\n" 1
reg: BORU8(reg,rc) "or $%0,%1,$%c\n" 1
reg: BXORI4(reg,rc) "xor $%0,%1,$%c\naddl $%c,0,$%c\n" 2
reg: BXORI8(reg,rc) "xor $%0,%1,$%c\n" 1
reg: BXORU4(reg,rc) "xor $%0,%1,$%c\n" 1
reg: BXORU8(reg,rc) "xor $%0,%1,$%c\n" 1
rc6: CNSTI4 "%a" range(a,0,63)
rc6: CNSTI8 "%a" range(a,0,63)
rc6: reg "$%0"
reg: LSHI4(reg,rc6) "sll $%0,%1,$%c\naddl $%c,0,$%c\n" 2
reg: LSHI8(reg,rc6) "sll $%0,%1,$%c\n" 1
reg: LSHU4(reg,rc6) "sll $%0,%1,$%c\nzap $%c,240,$%c\n" 2
reg: LSHU8(reg,rc6) "sll $%0,%1,$%c\n" 1
reg: RSHI4(reg,rc6) "sra $%0,%1,$%c\naddl $%c,0,$%c\n" 2
reg: RSHI8(reg,rc6) "sra $%0,%1,$%c\n" 1
reg: RSHU4(reg,rc6) "srl $%0,%1,$%c\n" 1
reg: RSHU8(reg,rc6) "srl $%0,%1,$%c\n" 1
reg: BCOMI4(reg) "not $%0,$%c\naddl $%c,0,$%c\n" 2
reg: BCOMU4(reg) "not $%0,$%c\nzap $%c,240,$%c\n" 2
reg: BCOMI8(reg) "not $%0,$%c\n" 1
reg: BCOMU8(reg) "not $%0,$%c\n" 1
reg: NEGI4(reg) "negl $%0,$%c\n" 1
reg: NEGI8(reg) "negq $%0,$%c\n" 1
reg: LOADI1(reg) "mov $%0,$%c\n" move(a)
reg: LOADI2(reg) "mov $%0,$%c\n" move(a)
reg: LOADI4(reg) "mov $%0,$%c\n" move(a)
reg: LOADI8(reg) "mov $%0,$%c\n" move(a)
reg: LOADP8(reg) "mov $%0,$%c\n" move(a)
reg: LOADU1(reg) "mov $%0,$%c\n" move(a)
reg: LOADU2(reg) "mov $%0,$%c\n" move(a)
reg: LOADU4(reg) "mov $%0,$%c\n" move(a)
reg: LOADU8(reg) "mov $%0,$%c\n" move(a)
reg: ADDF4(reg,reg) "adds $f%0,$f%1,$f%c\n" 1
reg: ADDF8(reg,reg) "addt $f%0,$f%1,$f%c\n" 1
reg: DIVF4(reg,reg) "divs $f%0,$f%1,$f%c\n" 1
reg: DIVF8(reg,reg) "divt $f%0,$f%1,$f%c\n" 1
reg: MULF4(reg,reg) "muls $f%0,$f%1,$f%c\n" 1
reg: MULF8(reg,reg) "mult $f%0,$f%1,$f%c\n" 1
reg: SUBF4(reg,reg) "subs $f%0,$f%1,$f%c\n" 1
reg: SUBF8(reg,reg) "subt $f%0,$f%1,$f%c\n" 1
reg: LOADF4(reg) "fmov $f%0,$f%c\n" move(a)
reg: LOADF8(reg) "fmov $f%0,$f%c\n" move(a)
reg: NEGF4(reg) "negs $f%0,$f%c\n" 1
reg: NEGF8(reg) "negt $f%0,$f%c\n" 1
reg: CVII4(reg) "sll $%0,8*(8-%a),$%c\nsra $%c,8*(8-%a),$%c\n" 2
reg: CVII8(reg) "sll $%0,8*(8-%a),$%c\nsra $%c,8*(8-%a),$%c\n" 2
reg: CVUI4(reg) "and $%0,(1<<(8*%a))-1,$%c\n" 1
reg: CVUI8(reg) "and $%0,(1<<(8*%a))-1,$%c\n" 1
reg: CVUU4(reg) "and $%0,(1<<(8*%a))-1,$%c\n" 1
reg: CVUU8(reg) "and $%0,(1<<(8*%a))-1,$%c\n" 1
reg: CVUP8(reg) "and $%0,(1<<(8*%a))-1,$%c\n" 1
reg: CVFF4(reg) "cvtts $f%0,$f%c\n" 1
reg: CVFF8(reg) "cvtst $f%0,$f%c\n" 1
reg: CVIF4(reg) "stq $%0,-56+%F($sp)\nldt $%f%c,-56+%F($sp)\ncvtqs $f%c,$f%c\n" 3
reg: CVIF8(reg) "stq $%0,-56+%F($sp)\nldt $%f%c,-56+%F($sp)\ncvtqt $f%c,$f%c\n" 3
reg: CVIF4(INDIRI4(addr)) "lds $f%c,%0\ncvtlq $f%c,$f%c\ncvtqs $f%c,$f%c\n" 3
reg: CVIF4(INDIRI8(addr)) "ldt $f%c,%0\ncvtqs $f%c,$f%c\n" 2
reg: CVIF8(INDIRI4(addr)) "lds $f%c,%0\ncvtlq $f%c,$f%c\ncvtqt $f%c,$f%c\n" 3
reg: CVIF8(INDIRI8(addr)) "ldt $f%c,%0\ncvtqt $f%c,$f%c\n" 2
reg: CVFI4(reg) "cvttqc $f%0,$f1\ncvtql $f1,$f1\nsts $f1,-56+%F($sp)\nldl $%c,-56+%F($sp)\n" 4
reg: CVFI8(reg) "cvttqc $f%0,$f1\nstt $f1,-56+%F($sp)\nldq $%c,-56+%F($sp)\n" 3
stmt: LABELV "%a:\n"
stmt: JUMPV(acon) "br %0\n" 1
stmt: JUMPV(reg) "jmp ($%0)\n" 1
stmt: EQI4(reg,rc6) "cmpeq $%0,%1,$23\nbne $23,%a\n" 2
stmt: EQU4(reg,rc6) "cmpeq $%0,%1,$23\nbne $23,%a\n" 2
stmt: EQI8(reg,rc6) "cmpeq $%0,%1,$23\nbne $23,%a\n" 2
stmt: EQU8(reg,rc6) "cmpeq $%0,%1,$23\nbne $23,%a\n" 2
stmt: NEI4(reg,rc6) "cmpeq $%0,%1,$23\nbeq $23,%a\n" 2
stmt: NEU4(reg,rc6) "cmpeq $%0,%1,$23\nbeq $23,%a\n" 2
stmt: NEI8(reg,rc6) "cmpeq $%0,%1,$23\nbeq $23,%a\n" 2
stmt: NEU8(reg,rc6) "cmpeq $%0,%1,$23\nbeq $23,%a\n" 2
stmt: GEI4(reg,rc6) "cmplt $%0,%1,$23\nbeq $23,%a\n" 2
stmt: GEI8(reg,rc6) "cmplt $%0,%1,$23\nbeq $23,%a\n" 2
stmt: GEU4(reg,rc6) "cmpult $%0,%1,$23\nbeq $23,%a\n" 1
stmt: GEU8(reg,rc6) "cmpult $%0,%1,$23\nbeq $23,%a\n" 1
stmt: GTI4(reg,rc6) "cmple $%0,%1,$23\nbeq $23,%a\n" 2
stmt: GTI8(reg,rc6) "cmple $%0,%1,$23\nbeq $23,%a\n" 2
stmt: GTU4(reg,rc6) "cmpule $%0,%1,$23\nbeq $23,%a\n" 1
stmt: GTU8(reg,rc6) "cmpule $%0,%1,$23\nbeq $23,%a\n" 1
stmt: LEI4(reg,rc6) "cmple $%0,%1,$23\nbne $23,%a\n" 2
stmt: LEI8(reg,rc6) "cmple $%0,%1,$23\nbne $23,%a\n" 2
stmt: LEU4(reg,rc6) "cmpule $%0,%1,$23\nbne $23,%a\n" 2
stmt: LEU8(reg,rc6) "cmpule $%0,%1,$23\nbne $23,%a\n" 2
stmt: LTI4(reg,rc6) "cmplt $%0,%1,$23\nbne $23,%a\n" 2
stmt: LTI8(reg,rc6) "cmplt $%0,%1,$23\nbne $23,%a\n" 2
stmt: LTU4(reg,rc6) "cmpult $%0,%1,$23\nbne $23,%a\n" 2
stmt: LTU8(reg,rc6) "cmpult $%0,%1,$23\nbne $23,%a\n" 2
stmt: EQF4(reg,reg) "cmpteq $f%0,$f%1,$f1\nfbne $f1,%a\n" 2
stmt: EQF8(reg,reg) "cmpteq $f%0,$f%1,$f1\nfbne $f1,%a\n" 2
stmt: LEF4(reg,reg) "cmptle $f%0,$f%1,$f1\nfbne $f1,%a\n" 2
stmt: LEF8(reg,reg) "cmptle $f%0,$f%1,$f1\nfbne $f1,%a\n" 2
stmt: LTF4(reg,reg) "cmptlt $f%0,$f%1,$f1\nfbne $f1,%a\n" 2
stmt: LTF8(reg,reg) "cmptlt $f%0,$f%1,$f1\nfbne $f1,%a\n" 2
stmt: NEF4(reg,reg) "cmpteq $f%0,$f%1,$f1\nfbeq $f1,%a\n" 2
stmt: NEF8(reg,reg) "cmpteq $f%0,$f%1,$f1\nfbeq $f1,%a\n" 2
stmt: GEF4(reg,reg) "cmptlt $f%0,$f%1,$f1\nfbeq $f1,%a\n" 2
stmt: GEF8(reg,reg) "cmptlt $f%0,$f%1,$f1\nfbeq $f1,%a\n" 2
stmt: GTF4(reg,reg) "cmptle $f%0,$f%1,$f1\nfbeq $f1,%a\n" 2
stmt: GTF8(reg,reg) "cmptle $f%0,$f%1,$f1\nfbeq $f1,%a\n" 2
ar: ADDRGP8 "%a"
ar: reg "($%0)"
reg: CALLF4(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
reg: CALLF8(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
reg: CALLI4(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
reg: CALLI8(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
reg: CALLP8(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
reg: CALLU4(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
reg: CALLU8(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
stmt: CALLV(ar) "jsr $26,%0\nldgp $gp,0($26)\n" 2
stmt: RETF4(reg) "# ret\n" 1
stmt: RETF8(reg) "# ret\n" 1
stmt: RETI4(reg) "# ret\n" 1
stmt: RETU4(reg) "# ret\n" 1
stmt: RETI8(reg) "# ret\n" 1
stmt: RETU8(reg) "# ret\n" 1
stmt: RETP8(reg) "# ret\n" 1
stmt: RETV(reg) "# ret\n" 1
stmt: ARGF4(reg) "# arg\n" 1
stmt: ARGF8(reg) "# arg\n" 1
stmt: ARGI4(reg) "# arg\n" 1
stmt: ARGI8(reg) "# arg\n" 1
stmt: ARGP8(reg) "# arg\n" 1
stmt: ARGU4(reg) "# arg\n" 1
stmt: ARGU8(reg) "# arg\n" 1
stmt: ARGB(INDIRB(reg)) "# argb %0\n" 1
stmt: ASGNB(reg,INDIRB(reg)) "# asgnb %0 %1\n" 1
%%
static void progend(void){}
static void progbeg(int argc, char *argv[]) {
int i;
{
union {
char c;
int i;
} u;
u.i = 0;
u.c = 1;
swap = ((int)(u.i == 1)) != IR->little_endian;
}
parseflags(argc, argv);
for (i = 0; i < 32; i++)
freg[i] = mkreg("%d", i, 1, FREG);
for (i = 0; i < 32; i++)
ireg[i] = mkreg("%d", i, 1, IREG);
ireg[29]->x.name = "gp";
ireg[30]->x.name = "sp";
fregw = mkwildcard(freg);
iregw = mkwildcard(ireg);
tmask[IREG] = INTTMP; tmask[FREG] = FLTTMP;
vmask[IREG] = INTVAR; vmask[FREG] = FLTVAR;
blkreg = mkreg("1", 1, 0xf, IREG);
}
static Symbol rmap(int opk) {
switch (optype(opk)) {
case I: case U: case P: case B:
return iregw;
case F:
return fregw;
default:
return 0;
}
}
static Symbol argreg(int offset, int ty) {
if (offset >= 48)
return NULL;
else if (ty == F)
return freg[(offset/8) + 16];
else
return ireg[(offset/8) + 16];
}
static void target(Node p) {
assert(p);
switch (specific(p->op)) {
case CNST+I: case CNST+U: case CNST+P:
if (range(p, 0, 0) == 0) {
setreg(p, ireg[31]);
p->x.registered = 1;
}
break;
case CNST+F:
if (p->syms[0]->u.c.v.d == 0) {
setreg(p, freg[31]);
p->x.registered = 1;
}
break;
case CALL+V:
rtarget(p, 0, ireg[27]);
break;
case CALL+F:
rtarget(p, 0, ireg[27]);
setreg(p, freg[0]);
break;
case CALL+I: case CALL+P: case CALL+U:
rtarget(p, 0, ireg[27]);
setreg(p, ireg[0]);
break;
case RET+F:
rtarget(p, 0, freg[0]);
break;
case RET+I: case RET+U: case RET+P:
rtarget(p, 0, ireg[0]);
break;
case ARG+F: case ARG+I: case ARG+P: case ARG+U: {
Symbol q = argreg(p->syms[2]->u.c.v.i, optype(p->op));
if (q)
rtarget(p, 0, q);
break;
}
case ASGN+B: rtarget(p->kids[1], 0, blkreg); break;
case ARG+B: rtarget(p->kids[0], 0, blkreg); break;
}
}
static void clobber(Node p) {
assert(p);
switch (specific(p->op)) {
case ASGN+I: case ASGN+U:
if (opsize(p->op) <= 2)
spill(1<<24, IREG, p);
break;
case DIV+I: case DIV+U: case MOD+I: case MOD+U:
spill(((1<<27)|(3<<24))&~p->syms[RX]->x.regnode->mask, IREG, p);
break;
case CALL+F:
spill(INTTMP | INTRET, IREG, p);
spill(FLTTMP, FREG, p);
break;
case CALL+I: case CALL+P: case CALL+U:
spill(INTTMP, IREG, p);
spill(FLTTMP | FLTRET, FREG, p);
break;
case CALL+V:
spill(INTTMP | INTRET, IREG, p);
spill(FLTTMP | FLTRET, FREG, p);
break;
}
}
static void emit2(Node p) {
int dst, n, src, sz, ty;
static int ty0;
Symbol q;
switch (specific(p->op)) {
case ARG+F: case ARG+I: case ARG+P: case ARG+U:
ty = optype(p->op);
sz = opsize(p->op);
q = argreg(p->syms[2]->u.c.v.i, ty);
src = getregnum(p->x.kids[0]);
if (q)
break;
else if (ty == F && sz == 4)
print("sts $f%d,%d($sp)\n", src, p->syms[2]->u.c.v.i - 48);
else if (ty == F && sz == 8)
print("stt $f%d,%d($sp)\n", src, p->syms[2]->u.c.v.i - 48);
else if (sz == 4)
print("stq $%d,%d($sp)\n", src, p->syms[2]->u.c.v.i - 48);
else if (sz == 8)
print("stq $%d,%d($sp)\n", src, p->syms[2]->u.c.v.i - 48);
else
assert(0);
break;
case ASGN+B:
dalign = salign = p->syms[1]->u.c.v.i;
blkcopy(getregnum(p->x.kids[0]), 0,
getregnum(p->x.kids[1]), 0,
p->syms[0]->u.c.v.i, tmpregs);
break;
case ARG+B: {
int doff = p->syms[2]->u.c.v.i, soff = 0, sreg = getregnum(p->x.kids[0]);
dalign = 8;
salign = p->syms[1]->u.c.v.i;
n = p->syms[0]->u.c.v.i;
for ( ; doff <= 40 && n > 0; doff += 8) {
print("uldq $%d,%d($%d)\n", (doff/8)+16, soff, sreg);
soff += 8;
n -= 8;
}
if (n > 0)
blkcopy(30, doff - 48, sreg, soff, n, tmpregs);
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