vectors.s

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/*=============================================================================
//
//	vectors.S
//
//	SPARC vectors and bootup code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): 	hmt
// Contributors:hmt
// Date:	1998-12-15
// Purpose:	SPARC vector code
// Description:	This file contains the code which hangs off SPARC vectors
//              including reset; it handles register under/overflow as well
//              as bootup, anything else is deferred to the default interrupt
//              or exception vsrs respectively.  See vec_[ix]vsr.S ...
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

!-----------------------------------------------------------------------------
	
//	.file	"vectors.S"

!-----------------------------------------------------------------------------
		
#include <pkgconf/system.h>	
#include <pkgconf/hal.h>

#include <pkgconf/hal_sparc.h>
#include CYGBLD_HAL_PLATFORM_H		// Platform config file

#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#else
# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
#endif
			
#if defined( CYGPKG_HAL_SPARCLITE_SIM ) || \
    defined( CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK ) || \
    defined( CYGPKG_HAL_SPARC_LEON ) || \
    defined( CYGPKG_HAL_SPARC_ERC32 )
#define BOOTUPSTACK_IS_INTERRUPTSTACK
#endif
	
//#define CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING

#ifndef CYGHWR_HAL_SPARC_HAS_ASR17
#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
#error Single Vector Trapping (SVT) demands ASR17 
#endif
#endif
	
#ifdef CYG_HAL_STARTUP_ROM
# ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING

! ROM startup and Single Vector Trapping demands a copy to RAM.
! Otherwise it may be configured in, but it is not required.
	
#  ifndef CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
#   define CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
#  endif

# endif
#endif

!------------------------------------------------------------------------

#include <cyg/hal/vectors.h>

#define DELAYS_AFTER_WRPSR_SAME_WINDOW
#define DELAYS_AFTER_WRWIM

!------------------------------------------------------------------------

#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING

	.macro	VECTOR_EXCEPTION
	.p2align 4
	rd	%tbr, %l3
	rd	%psr, %l0
	ba	__entry_exception
	 and	%l3, TT_MASK, %l4
	.endm
	
	.macro	VECTOR_INTERRUPT level
	.p2align 4
	rd	%psr, %l0
	mov	\level << 2, %l5
	ba	__entry_interrupt
	 mov	\level << 4, %l4
	.endm
	
	.macro	VECTOR_CODE_WIM name
	.p2align 4
	ba	__entry_\name
	 rd	%wim, %l0
	.endm
	
#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING

!------------------------------------------------------------------------
! The start of the code; this is the entry point:
	
	.section ".vectors","ax"

	.global rom_vectors
rom_vectors:
	.global	reset_vector
reset_vector:	
	! this code goes to the real reset handler, it will be
	! overwritten by the start of vectoring handler...
	b	genuine_reset
	nop
	! usually drop through to:
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
	ba	__entry_exception	! reset becomes an exception
	 and	%l3, TT_MASK, %l4	! once we are running
	
	VECTOR_EXCEPTION	 	!   1
	VECTOR_EXCEPTION	 	!   2
	VECTOR_EXCEPTION	 	!   3
	VECTOR_EXCEPTION	 	!   4
	
	VECTOR_CODE_WIM wover	 	!   5 window overflow
	VECTOR_CODE_WIM wunder		!   6 window underflow
	VECTOR_EXCEPTION		!   7
	VECTOR_EXCEPTION		!   8
	VECTOR_EXCEPTION		!   9

	VECTOR_EXCEPTION		!  10
	VECTOR_EXCEPTION		!  11
	VECTOR_EXCEPTION		!  12
	VECTOR_EXCEPTION		!  13
	VECTOR_EXCEPTION		!  14
	
	VECTOR_EXCEPTION		!  15
	VECTOR_EXCEPTION		!  16
	VECTOR_INTERRUPT  1		!  17 interrupt_level_1
	VECTOR_INTERRUPT  2		!  18 interrupt_level_2
	VECTOR_INTERRUPT  3		!  19 interrupt_level_3
	
	VECTOR_INTERRUPT  4		!  20 interrupt_level_4
	VECTOR_INTERRUPT  5		!  21 interrupt_level_5
	VECTOR_INTERRUPT  6		!  22 interrupt_level_6
	VECTOR_INTERRUPT  7		!  23 interrupt_level_7
	VECTOR_INTERRUPT  8		!  24 interrupt_level_8
	
	VECTOR_INTERRUPT  9		!  25 interrupt_level_9
	VECTOR_INTERRUPT 10		!  26 interrupt_level_10
	VECTOR_INTERRUPT 11		!  27 interrupt_level_11
	VECTOR_INTERRUPT 12		!  28 interrupt_level_12
	VECTOR_INTERRUPT 13		!  29 interrupt_level_13
	
	VECTOR_INTERRUPT 14		!  30 interrupt_level_14
	VECTOR_INTERRUPT 15		!  31 interrupt_level_15
	VECTOR_EXCEPTION		!  32
	VECTOR_EXCEPTION		!  33
	VECTOR_EXCEPTION		!  34

	VECTOR_EXCEPTION		!  35
	VECTOR_EXCEPTION		!  36
	VECTOR_EXCEPTION		!  37
	VECTOR_EXCEPTION		!  38
	VECTOR_EXCEPTION		!  39
	
	.rept 216			! 40-255 is 216 of them
	VECTOR_EXCEPTION		! whichever
	.endr
#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING

#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
real_vector:
	! here,locals have been set up as follows:
	! %l0 = psr
	! %l1 = pc	
	! %l2 = npc
	! %l3 = tbr
	and	%l3, TT_IS_INTR_MASK, %l4
	cmp	%l4, TT_IS_INTR_VALUE
	bne	not_an_interrupt	! delay slot does not matter
	! here be the pre-vector interrupt handler
interrupt:
	and	%l3, 0x0f0, %l4		! get an interrupt number out
	srl	%l4, 2, %l5		! to a word address offset
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
__entry_interrupt:
	sethi	%hi(hal_vsr_table), %l6
	or	%l6, %lo(hal_vsr_table), %l6
	ld	[ %l6 + %l5 ], %l6	! get vector in %l6
	jmp	%l6			! and go there
	srl	%l4, 4, %l3		! vector number into %l3: so that
					! interrupts and exceptions/traps
					! have the same API to VSRs

#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
not_an_interrupt:
	and	%l3, TT_MASK, %l4
	cmp	%l4, (TRAP_WUNDER << TT_SHL)

	bne,a	not_window_underflow
	cmp	%l4, (TRAP_WOVER << TT_SHL)	! (if taken)

	! here be the window underflow handler:
window_underflow:
	! CWP is trap handler
	! CWP + 1 is trapped RESTORE instruction
	! CWP + 2 is invalid context which must be restored
	! CWP + 3 is next invalid context

	wr	%l0, %psr		! restore the condition flags
					! (CWP is unchanged)
	! the following instructions delay enough; no need for NOPs
	rd	%wim, %l0		! get the wim
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
__entry_wunder:	
	sll	%l0, 1, %l3		! Rotate wim left
	srl	%l0, __WINSIZE-1, %l0
	wr	%l0, %l3, %wim		! Install the new wim

#ifdef DELAYS_AFTER_WRWIM
	nop				! are these delays needed?
	nop				! (following restore uses wim)
	nop
#endif
	restore				! Users window
	restore				! Her callers window (now valid)
	
	ldd	[%sp + 0 * 4], %l0	! restore L & I registers
	ldd	[%sp + 2 * 4], %l2
	ldd	[%sp + 4 * 4], %l4
	ldd	[%sp + 6 * 4], %l6

	ldd	[%sp + 8 * 4], %i0
	ldd	[%sp + 10 * 4], %i2
	ldd	[%sp + 12 * 4], %i4