hal_arch.h

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//==========================================================================
//
//      hal_arch.h
//
//      Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// for more details.
//
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
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// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    sfurman
// Contributors: 
// Date:         2003-01-17
// Purpose:      Define architecture abstractions
// Usage:        #include <cyg/hal/hal_arch.h>
//              
//####DESCRIPTIONEND####
//
//==========================================================================

#ifndef CYGONCE_HAL_HAL_ARCH_H
#define CYGONCE_HAL_HAL_ARCH_H

// Include macros to access special-purpose registers (SPRs)
#include <cyg/hal/spr_defs.h>

#define CYG_HAL_OPENRISC_REG_SIZE 4

#ifndef __ASSEMBLER__
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

//--------------------------------------------------------------------------
// Processor saved states:
// The layout of this structure is also defined in "arch.inc", for assembly
// code. Do not change this without changing that (or vice versa).

#define CYG_HAL_OPENRISC_REG CYG_WORD32

typedef struct 
{
    // These are common to all saved states
    CYG_HAL_OPENRISC_REG    r[32];          // GPR regs
    CYG_HAL_OPENRISC_REG    machi;          // High and low words of
    CYG_HAL_OPENRISC_REG    maclo;          //   multiply/accumulate reg
    
    // These are only saved for exceptions and interrupts
    CYG_WORD32              vector;         /* Vector number            */
    CYG_WORD32              sr;             /* Status Reg               */
    CYG_HAL_OPENRISC_REG    pc;             /* Program Counter          */

    // Saved only for exceptions, and not restored when continued:
    // Effective address of instruction/data access that caused exception
    CYG_HAL_OPENRISC_REG    eear;           /* Exception effective address reg */
} HAL_SavedRegisters;

//--------------------------------------------------------------------------
//  Utilities

// Move from architecture special register (SPR)
#define MFSPR(_spr_)                                      \
({  CYG_HAL_OPENRISC_REG _result_;                        \
    asm volatile ("l.mfspr %0, r0, %1;"                   \
        : "=r"(_result_)                                  \
        : "K"(_spr_)                                      \
    );                                                    \
    _result_;})

// Move data to architecture special registers (SPR)
#define MTSPR(_spr_, _val_)                               \
CYG_MACRO_START                                           \
    CYG_HAL_OPENRISC_REG val = _val_;                     \
    asm volatile ("l.mtspr r0, %0, %1;"                   \
        :                                                 \
        : "r"(val), "K"(_spr_)                            \
    );                                                    \
CYG_MACRO_END

//--------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.

externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );

//--------------------------------------------------------------------------
// Bit manipulation macros

externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);

#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);

// NOTE - Below can be optimized with l.ff1 instruction if that optional
//        instruction is implemented in HW.  OR12k does not implement
//        it at this time, however.
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);

//--------------------------------------------------------------------------
// Context Initialization


// Initialize the context of a thread.
// Arguments:
// _sparg_ name of variable containing current sp, will be written with new sp
// _thread_ thread object address, passed as argument to entry point
// _entry_ entry point address.
// _id_ bit pattern used in initializing registers, for debugging.
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )                     \
{                                                                                       \
    int _i_;                                                                            \
    register CYG_WORD _sp_ = ((CYG_WORD)_sparg_);                                       \
    register HAL_SavedRegisters *_regs_;                                                \
    _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\
    _sp_ &= ~(CYGARC_ALIGNMENT);                                                        \
    for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_;                      \
    (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_);       /* SP = top of stack      */   \
    (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_);       /* FP = top of stack      */   \
    (_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_);   /* R3 = arg1 = thread ptr */   \
    (_regs_)->maclo = 0;                                 /* MACLO = 0              */   \
    (_regs_)->machi = 0;                                 /* MACHI = 0              */   \
    (_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE);              /* Interrupts enabled     */   \
    (_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_);      /* PC = entry point       */   \
    (_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_);    /* PC = entry point       */   \
    _sparg_ = (CYG_ADDRESS)_regs_;                                                      \
}

//--------------------------------------------------------------------------
// Context switch macros.

// The arguments to these macros are *pointers* to locations where the
// stack pointer of the thread is to be stored/retrieved, i.e. *not*
// the value of the stack pointer itself.

externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
externC void hal_thread_load_context( CYG_ADDRESS to )
    __attribute__ ((noreturn));

#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
        hal_thread_switch_context( (CYG_ADDRESS)_tspptr_,               \
                                   (CYG_ADDRESS)_fspptr_);

#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );

// Translate a stack pointer as saved by the thread context macros above into
// a pointer to a HAL_SavedRegisters structure.
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )  \
        (_regs_) = (HAL_SavedRegisters *)(_sp_)

//--------------------------------------------------------------------------