📄 hal_intr.h
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// Enable both tick timer and external interrupts in the Supervisor Register
#define HAL_ENABLE_INTERRUPTS() \
MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_IEE|SPR_SR_TEE))
// Copy interrupt flags from argument into Supervisor Register
#define HAL_RESTORE_INTERRUPTS(_old_) \
CYG_MACRO_START \
cyg_uint32 t1,t2; \
t1 = MFSPR(SPR_SR) & ~(SPR_SR_IEE|SPR_SR_TEE); \
t2 = (_old_) & (SPR_SR_IEE|SPR_SR_TEE); \
MTSPR(SPR_SR, t1 | t2); \
CYG_MACRO_END
#define HAL_QUERY_INTERRUPTS( _state_ ) \
CYG_MACRO_START \
_state = MFSPR(SPR_SR); \
CYG_MACRO_END
#endif // CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
//--------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
hal_interrupt_stack_call_pending_DSRs()
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
// use them to declare these extern however you want:
// extern char HAL_INTERRUPT_STACK_BASE[];
// extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif
//--------------------------------------------------------------------------
// Vector translation.
// For chained interrupts we only have a single vector though which all
// are passed. For unchained interrupts we have a vector per interrupt.
#ifndef HAL_TRANSLATE_VECTOR
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
#else
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
#endif
#endif
//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
(_state_) = 0; \
else \
(_state_) = 1; \
CYG_MACRO_END
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
{ \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
{ \
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
} \
}
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
{ \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
{ \
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
hal_interrupt_data[_index_] = 0; \
hal_interrupt_objects[_index_] = 0; \
} \
}
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
*(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
if( (void*)_poldvsr_ != NULL) \
*(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
CYG_MACRO_END
// This is an ugly name, but what it means is: grab the VSR back to eCos
// internal handling, or if you like, the default handler. But if
// cooperating with GDB and CygMon, the default behaviour is to pass most
// exceptions to CygMon. This macro undoes that so that eCos handles the
// exception. So use it with care.
externC void cyg_hal_default_exception_vsr(void);
externC void cyg_hal_default_interrupt_vsr(void);
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \
? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
: (CYG_ADDRESS)cyg_hal_default_exception_vsr, \
_poldvsr_ ); \
CYG_MACRO_END
//--------------------------------------------------------------------------
// Interrupt controller access
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
// Mask (disable) interrupts from specified source
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
int mask; \
if ((_vector_) == CYGNUM_HAL_INTERRUPT_RTC) { \
/* The tick timer interrupt isn't */ \
/* controlled by the PIC; It has its own*/\
/* enable bit in the SR. */ \
MTSPR(SPR_SR, MFSPR(SPR_SR)& ~SPR_SR_TEE);\
} else { \
mask = ~(1 << (_vector_)); \
MTSPR(SPR_PICMR, MFSPR(SPR_PICMR)& mask); \
} \
CYG_MACRO_END
// Allow interrupts from specified source
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
int bit; \
if ((_vector_) == CYGNUM_HAL_INTERRUPT_RTC) { \
/* The tick timer interrupt isn't */ \
/* controlled by the PIC; It has its own*/\
/* enable bit in the SR. */ \
MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_TEE);\
} else { \
bit = (1 << (_vector_)); \
MTSPR(SPR_PICMR, MFSPR(SPR_PICMR) | bit); \
} \
CYG_MACRO_END
// Reset interrupt request in the PIC for specified device
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
int mask; \
if ((_vector_) != CYGNUM_HAL_INTERRUPT_RTC) { \
mask = ~(1 << (_vector_)); \
MTSPR(SPR_PICSR, MFSPR(SPR_PICSR) & mask);\
} \
CYG_MACRO_END
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) CYG_EMPTY_STATEMENT
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) CYG_EMPTY_STATEMENT
#endif
//--------------------------------------------------------------------------
// Clock control.
externC CYG_WORD32 cyg_hal_clock_period;
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
// Start tick timer interrupts
#define HAL_CLOCK_INITIALIZE( _period_ ) \
CYG_MACRO_START \
{ \
int ttmr_new = _period_ | 0x60000000; \
MTSPR(SPR_TTMR, 0); \
MTSPR(SPR_TTCR, 0); \
MTSPR(SPR_TTMR, ttmr_new); \
cyg_hal_clock_period = _period_; \
} \
CYG_MACRO_END
// Acknowledge clock timer interrupt
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
CYG_MACRO_START \
int ttmr_new = _period_ | 0x60000000; \
MTSPR(SPR_TTMR, ttmr_new); \
CYG_MACRO_END
// Read the current value of the tick timer
#define HAL_CLOCK_READ( _pvalue_ ) \
CYG_MACRO_START \
*(_pvalue_) = MFSPR(SPR_TTCR); \
CYG_MACRO_END
#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
!defined(HAL_CLOCK_LATENCY)
#define HAL_CLOCK_LATENCY( _pvalue_ ) \
CYG_MACRO_START \
register CYG_WORD32 _cval_; \
HAL_CLOCK_READ(&_cval_); \
*(_pvalue_) = _cval_ - cyg_hal_clock_period; \
CYG_MACRO_END
#endif
//--------------------------------------------------------------------------
// Microsecond delay function provided in hal_misc.c
externC void hal_delay_us(int us);
#define HAL_DELAY_US(n) hal_delay_us(n)
#endif /* #ifndef __ASSEMBLER__ */
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
// End of hal_intr.h
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