hal_cpu.h

开放源码实时操作系统源码.

#define FR_FREG30 (FR_FREG29 + FPR_SIZE)
#define FR_FREG31 (FR_FREG30 + FPR_SIZE)

#define FR_Y      (FR_FREG31 + FPR_SIZE)
#define FR_PSR    (FR_Y      + GPR_SIZE)
#define FR_WIM    (FR_PSR    + GPR_SIZE)
#define FR_TBR    (FR_WIM    + GPR_SIZE)
#define FR_PC     (FR_TBR    + GPR_SIZE)
#define FR_NPC    (FR_PC     + GPR_SIZE)
#define FR_FPSR   (FR_NPC    + GPR_SIZE)
#define FR_CPSR   (FR_FPSR   + GPR_SIZE)
#define FR_DIA1   (FR_CPSR   + GPR_SIZE)
#define FR_DIA2   (FR_DIA1   + GPR_SIZE)
#define FR_DDA1   (FR_DIA2   + GPR_SIZE)
#define FR_DDA2   (FR_DDA1   + GPR_SIZE)
#define FR_DDV1   (FR_DDA2   + GPR_SIZE)
#define FR_DDV2   (FR_DDV1   + GPR_SIZE)
#define FR_DCR    (FR_DDV2   + GPR_SIZE)
#define FR_DSR    (FR_DCR    + GPR_SIZE)
#define FR_ASR17  (FR_DSR    + GPR_SIZE)

#define EX_STACK_SIZE (FR_ASR17 + GPR_SIZE)

#ifndef __ASSEMBLER__
/*
 *  How registers are stored for exceptions.
 */
typedef struct
{
    unsigned long _g0;
    unsigned long _g1;
    unsigned long _g2;
    unsigned long _g3;
    unsigned long _g4;
    unsigned long _g5;
    unsigned long _g6;
    unsigned long _g7;
    unsigned long _o0;
    unsigned long _o1;
    unsigned long _o2;
    unsigned long _o3;
    unsigned long _o4;
    unsigned long _o5;
    unsigned long _sp;
    unsigned long _o7;
    unsigned long _l0;
    unsigned long _l1;
    unsigned long _l2;
    unsigned long _l3;
    unsigned long _l4;
    unsigned long _l5;
    unsigned long _l6;
    unsigned long _l7;
    unsigned long _i0;
    unsigned long _i1;
    unsigned long _i2;
    unsigned long _i3;
    unsigned long _i4;
    unsigned long _i5;
    unsigned long _fp;
    unsigned long _i7;

    unsigned long _fpr[32];

    unsigned long _y;
    unsigned long _psr;
    unsigned long _wim;
    unsigned long _tbr;

    unsigned long _pc;
    unsigned long _npc;
    unsigned long _fpsr;
    unsigned long _cpsr;
    unsigned long _dia1;
    unsigned long _dia2;
    unsigned long _dda1;
    unsigned long _dda2;
    unsigned long _ddv1;
    unsigned long _ddv2;
    unsigned long _dcr;
    unsigned long _dsr;

    unsigned long _asr17;

} ex_regs_t;

/*
 *  How gdb expects registers to be stored.
 */
typedef struct
{
    unsigned long _g0;
    unsigned long _g1;
    unsigned long _g2;
    unsigned long _g3;
    unsigned long _g4;
    unsigned long _g5;
    unsigned long _g6;
    unsigned long _g7;
    unsigned long _o0;
    unsigned long _o1;
    unsigned long _o2;
    unsigned long _o3;
    unsigned long _o4;
    unsigned long _o5;
    unsigned long _sp;
    unsigned long _o7;
    unsigned long _l0;
    unsigned long _l1;
    unsigned long _l2;
    unsigned long _l3;
    unsigned long _l4;
    unsigned long _l5;
    unsigned long _l6;
    unsigned long _l7;
    unsigned long _i0;
    unsigned long _i1;
    unsigned long _i2;
    unsigned long _i3;
    unsigned long _i4;
    unsigned long _i5;
    unsigned long _fp;
    unsigned long _i7;
    unsigned long _fpr[32];
    unsigned long _y;
    unsigned long _psr;
    unsigned long _wim;
    unsigned long _tbr;
    unsigned long _pc;
    unsigned long _npc;
    unsigned long _fpsr;
    unsigned long _cpsr;
    unsigned long _dia1;
    unsigned long _dia2;
    unsigned long _dda1;
    unsigned long _dda2;
    unsigned long _ddv1;
    unsigned long _ddv2;
    unsigned long _dcr;
    unsigned long _dsr;
} gdb_regs_t;


extern void __dcache_flush(void *addr, int nbytes);
extern void __icache_flush(void *addr, int nbytes);
extern int  __dcache_disable(void);
extern void __dcache_enable(void);
extern void __icache_disable(void);
extern void __icache_enable(void);


#endif /* !__ASSEMBLER__ */


#define PSR_INIT 0xfa7


/*
 * Memory-mapped (ASI=1) registers for MB8683x series.
 */
#define CBIR    0x00000000
#define LCR     0x00000004
#define LCSR    0x00000008
#define CSR     0x0000000C
#define RLCR    0x00000010
#define BCR     0x00000020
#define SSCR    0x00000080

#define SPGMR   0x00000120
#define ARSR1   0x00000124
#define ARSR2   0x00000128
#define ARSR3   0x0000012C
#define ARSR4   0x00000130
#define ARSR5   0x00000134
#define AMR0    0x00000140
#define AMR1    0x00000144
#define AMR2    0x00000148
#define AMR3    0x0000014C
#define AMR4    0x00000150
#define AMR5    0x00000154
#define WSSR0   0x00000160
#define WSSR1   0x00000164
#define WSSR2   0x00000168
#define BWCR    0x0000016C
#define REFTMR  0x00000174
#define DRLD    0x00000178
#define VER2    0x00020000
#define SLPMD   0x00020004

/* CBIR bit fields */
#define CBIR_ICEN    0x01  /* Icache enable */
#define CBIR_ICLOCK  0x02  /* Icache lock   */
#define CBIR_DCEN    0x04  /* Dcache enable */
#define CBIR_DCLOCK  0x08  /* Dcache lock   */
#define CBIR_PBEN    0x10  /* Prefetch Buffer enable */
#define CBIR_WBEN    0x20  /* Write Buffer enable */

/* LCR bit fields */
#define LCR_ILOCK    0x01  /* Icache Auto-lock enable */
#define LCR_DLOCK    0x02  /* Dcache Auto-lock enable */

/* WSSRn bit fields */
#define WSSR_OVERRIDE 1
#define WSSR_SINGLE   2
#define WSSR_WAITEN   4

#define WSSR_CNT1_SHIFT 8
#define WSSR_CNT2_SHIFT 3
#define WSSR_CS0_SHIFT  6
#define WSSR_CS1_SHIFT  19

#define WSSR_SUBVAL(c1,c2,flags) (((c1)<<8)|((c2)<<3)|(flags))
#define WSSR_VAL(c1b,c2b,flagsb,c1a,c2a,flagsa) \
           ((WSSR_SUBVAL(c1b,c2b,flagsb)<<19)|(WSSR_SUBVAL(c1a,c2a,flagsa)<<6))

#define SPGMR_VAL(asi,addr) (((asi)<<23)|(((addr)>>9)&0x007ffffe))
#define ARSR_VAL(asi,base)  ((((asi)&0xff)<<23)|(((base)>>9)&0x007ffffe))
#define AMR_VAL(asi,base)   (((~(asi))<<23)|(((~(base))>>9)&0x007fffff))

/* SSCR bit fields */
#define SSCR_TIMER  0x04
#define SSCR_WAIT   0x08
#define SSCR_CS     0x10
#define SSCR_SAMEPG 0x20
#define SSCR_DRAM   0x40
#define SSCR_BURST  0x80

/* BCR bit fields */
#define BCR_IBE   1
#define BCR_DBE   2


/* DRAM Controller registers as offsets into CS3 space */
#define DBANKR  0x20
#define DTIMR   0x24

/* DBANKR bit fields */
#define DBANKR_512K     0
#define DBANKR_1M       1
#define DBANKR_2M       2
#define DBANKR_4M       3
#define DBANKR_8M       4
#define DBANKR_16M      5
#define DBANKR_32M      6
#define DBANKR_64M      7
#define DBANKR_CA9      (2<<4)
#define DBANKR_CA10     (3<<4)
#define DBANKR_CA11     (4<<4)
#define DBANKR_CA12     (5<<4)
#define DBANKR_4C1W     (0<<7)  /* 4CAS/1WE */
#define DBANKR_1C4W     (1<<7)  /* 1CAS/4WE */
#define DBANKR_EDO      (1<<8)
#define DBANKR_SA01     (1<<9)
#define DBANKR_SA02     (2<<9)
#define DBANKR_SA04     (3<<9)

/* DTIMR bit fields */
#define DTIMR_RP1     0
#define DTIMR_RP2     1
#define DTIMR_CAS1    (0<<1)
#define DTIMR_CAS2    (1<<1)
#define DTIMR_CBR1    (0<<2)
#define DTIMR_CBR2    (1<<2)
#define DTIMR_CBR3    (2<<2)
#define DTIMR_RPS2    (0<<4)
#define DTIMR_RPS4    (1<<4)


/* -------------------------------------------------------------------*/
#endif  /* CYGONCE_HAL_SPARCLITE_HAL_CPU_H */
/* EOF hal_cpu.h */