📄 hal_cpu.h
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#ifndef CYGONCE_HAL_SPARCLITE_HAL_CPU_H
#define CYGONCE_HAL_SPARCLITE_HAL_CPU_H
// ====================================================================
//
// hal_cpu.h
//
// HAL CPU architecture file for MB8683x
//
// ====================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Red Hat
// Contributors: Red Hat, hmt
// Date: 1999-03-01
// Purpose: MB8683x SPARClite CPU symbols
// Description:
//
//####DESCRIPTIONEND####
//
// ====================================================================
// NOTE: THIS FILE HAS NOT BEEN "CLEANED UP" WRT NAMESPACE USE
//
// it is only used internally to the SLEB HAL
//
// it should not be exported by inclusion in API header files
//
#ifndef __ASSEMBLER__
/*
* Register numbers. These are assumed to match the
* register numbers used by GDB.
*/
enum __regnames {
REG_G0, REG_G1, REG_G2, REG_G3,
REG_G4, REG_G5, REG_G6, REG_G7,
REG_O0, REG_O1, REG_O2, REG_O3,
REG_O4, REG_O5, REG_SP, REG_O7,
REG_L0, REG_L1, REG_L2, REG_L3,
REG_L4, REG_L5, REG_L6, REG_L7,
REG_I0, REG_I1, REG_I2, REG_I3,
REG_I4, REG_I5, REG_FP, REG_I7,
REG_F0, REG_F1, REG_F2, REG_F3,
REG_F4, REG_F5, REG_F6, REG_F7,
REG_F8, REG_F9, REG_F10, REG_F11,
REG_F12, REG_F13, REG_F14, REG_F15,
REG_F16, REG_F17, REG_F18, REG_F19,
REG_F20, REG_F21, REG_F22, REG_F23,
REG_F24, REG_F25, REG_F26, REG_F27,
REG_F28, REG_F29, REG_F30, REG_F31,
REG_Y, REG_PSR, REG_WIM, REG_TBR,
REG_PC, REG_NPC, REG_FPSR, REG_CPSR,
REG_DIA1, REG_DIA2, REG_DDA1, REG_DDA2,
REG_DDV1, REG_DDV2, REG_DCR, REG_DSR,
REG_LAST
};
#endif
#ifdef __ASSEMBLER__
/*
* Macros to glue together two tokens.
*/
#ifdef __STDC__
#define XGLUE(a,b) a##b
#else
#define XGLUE(a,b) a/**/b
#endif
#define GLUE(a,b) XGLUE(a,b)
#ifdef NEED_UNDERSCORE
#define SYM_NAME(name) GLUE(_,name)
.macro FUNC_START name
.align 4
.globl _\name
.type _\name,#function
.proc 04
_\name:
.endm
.macro FUNC_END name
.LL_\name:
.size _\name,.LL_\name - _\name
.endm
#else
#define SYM_NAME(name) name
.macro FUNC_START name
.align 4
.globl \name
.type \name,#function
.proc 04
\name:
.endm
.macro FUNC_END name
.LL\name:
.size \name,.LL\name - \name
.endm
#endif
#endif /* __ASSEMBLER__ */
/*
* breakpoint opcode.
*/
#define BREAKPOINT_OPCODE 0x91d02001
/*
* inline asm statement to cause breakpoint.
*/
#define BREAKPOINT() asm volatile ("ta 1\n")
/*
* Core Exception vectors.
*/
#define BSP_EXC_IACCESS 0
#define BSP_EXC_ILL 1
#define BSP_EXC_IPRIV 2
#define BSP_EXC_FPDIS 3
#define BSP_EXC_WINOVF 4
#define BSP_EXC_WINUND 5
#define BSP_EXC_ALIGN 6
#define BSP_EXC_DACCESS 7
#define BSP_EXC_TAGOVF 8
#define BSP_EXC_INT1 9
#define BSP_EXC_INT2 10
#define BSP_EXC_INT3 11
#define BSP_EXC_INT4 12
#define BSP_EXC_INT5 13
#define BSP_EXC_INT6 14
#define BSP_EXC_INT7 15
#define BSP_EXC_INT8 16
#define BSP_EXC_INT9 17
#define BSP_EXC_INT10 18
#define BSP_EXC_INT11 19
#define BSP_EXC_INT12 20
#define BSP_EXC_INT13 21
#define BSP_EXC_INT14 22
#define BSP_EXC_INT15 23
#define BSP_EXC_CPDIS 24
#define BSP_EXC_BREAK 25
#define BSP_EXC_WINFLUSH 26
#define BSP_EXC_SYSCALL 27
#define BSP_EXC_DEBUG 28
#define BSP_EXC_TRAP 29
#define BSP_MAX_EXCEPTIONS 30
#define BSP_VEC_MT_DEBUG 30
#define BSP_VEC_STUB_ENTRY 31
#define BSP_VEC_BSPDATA 32
#define NUM_VTAB_ENTRIES 33
#define CPU_WINSIZE 8
/*
* Exception frame offsets.
*/
#define GPR_SIZE 4
#define FPR_SIZE 4
#define PTR_BYTES 4
/* Leave room for locals + hidden arg + arg spill + dword align */
#define FR_BIAS ((16+1+6+1)*GPR_SIZE)
#define FR_G0 FR_BIAS
#define FR_G1 (FR_G0 + GPR_SIZE)
#define FR_G2 (FR_G1 + GPR_SIZE)
#define FR_G3 (FR_G2 + GPR_SIZE)
#define FR_G4 (FR_G3 + GPR_SIZE)
#define FR_G5 (FR_G4 + GPR_SIZE)
#define FR_G6 (FR_G5 + GPR_SIZE)
#define FR_G7 (FR_G6 + GPR_SIZE)
#define FR_O0 (FR_G7 + GPR_SIZE)
#define FR_O1 (FR_O0 + GPR_SIZE)
#define FR_O2 (FR_O1 + GPR_SIZE)
#define FR_O3 (FR_O2 + GPR_SIZE)
#define FR_O4 (FR_O3 + GPR_SIZE)
#define FR_O5 (FR_O4 + GPR_SIZE)
#define FR_O6 (FR_O5 + GPR_SIZE)
#define FR_SP FR_O6
#define FR_O7 (FR_SP + GPR_SIZE)
#define FR_L0 (FR_O7 + GPR_SIZE)
#define FR_L1 (FR_L0 + GPR_SIZE)
#define FR_L2 (FR_L1 + GPR_SIZE)
#define FR_L3 (FR_L2 + GPR_SIZE)
#define FR_L4 (FR_L3 + GPR_SIZE)
#define FR_L5 (FR_L4 + GPR_SIZE)
#define FR_L6 (FR_L5 + GPR_SIZE)
#define FR_L7 (FR_L6 + GPR_SIZE)
#define FR_I0 (FR_L7 + GPR_SIZE)
#define FR_I1 (FR_I0 + GPR_SIZE)
#define FR_I2 (FR_I1 + GPR_SIZE)
#define FR_I3 (FR_I2 + GPR_SIZE)
#define FR_I4 (FR_I3 + GPR_SIZE)
#define FR_I5 (FR_I4 + GPR_SIZE)
#define FR_I6 (FR_I5 + GPR_SIZE)
#define FR_FP FR_I6
#define FR_I7 (FR_FP + GPR_SIZE)
#define FR_FREG0 (FR_I7 + GPR_SIZE)
#define FR_FREG1 (FR_FREG0 + FPR_SIZE)
#define FR_FREG2 (FR_FREG1 + FPR_SIZE)
#define FR_FREG3 (FR_FREG2 + FPR_SIZE)
#define FR_FREG4 (FR_FREG3 + FPR_SIZE)
#define FR_FREG5 (FR_FREG4 + FPR_SIZE)
#define FR_FREG6 (FR_FREG5 + FPR_SIZE)
#define FR_FREG7 (FR_FREG6 + FPR_SIZE)
#define FR_FREG8 (FR_FREG7 + FPR_SIZE)
#define FR_FREG9 (FR_FREG8 + FPR_SIZE)
#define FR_FREG10 (FR_FREG9 + FPR_SIZE)
#define FR_FREG11 (FR_FREG10 + FPR_SIZE)
#define FR_FREG12 (FR_FREG11 + FPR_SIZE)
#define FR_FREG13 (FR_FREG12 + FPR_SIZE)
#define FR_FREG14 (FR_FREG13 + FPR_SIZE)
#define FR_FREG15 (FR_FREG14 + FPR_SIZE)
#define FR_FREG16 (FR_FREG15 + FPR_SIZE)
#define FR_FREG17 (FR_FREG16 + FPR_SIZE)
#define FR_FREG18 (FR_FREG17 + FPR_SIZE)
#define FR_FREG19 (FR_FREG18 + FPR_SIZE)
#define FR_FREG20 (FR_FREG19 + FPR_SIZE)
#define FR_FREG21 (FR_FREG20 + FPR_SIZE)
#define FR_FREG22 (FR_FREG21 + FPR_SIZE)
#define FR_FREG23 (FR_FREG22 + FPR_SIZE)
#define FR_FREG24 (FR_FREG23 + FPR_SIZE)
#define FR_FREG25 (FR_FREG24 + FPR_SIZE)
#define FR_FREG26 (FR_FREG25 + FPR_SIZE)
#define FR_FREG27 (FR_FREG26 + FPR_SIZE)
#define FR_FREG28 (FR_FREG27 + FPR_SIZE)
#define FR_FREG29 (FR_FREG28 + FPR_SIZE)
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