mcf5272_devs.h

开放源码实时操作系统源码.

    // UART transmitter FIFO register
    cyg_uint8 utf;

    // Gap
    cyg_uint8 _res11[3];

    // UART receiver FIFO register
    cyg_uint8 urf;

    // Gap
    cyg_uint8 _res12[3];

    // UART fractional precision divider register
    cyg_uint8 ufpd;

    // Gap
    cyg_uint8 _res13[3];

    // UART input port register
    cyg_uint8 uip;

    // Gap
    cyg_uint8 _res14[3];

    // UART output port register 1
    cyg_uint8 uop1;

    // Gap
    cyg_uint8 _res15[3];

    // UART output port register 0
    cyg_uint8 uop0;

    // Gap
    cyg_uint8 _res16[3];

} __attribute__ ((aligned (4), packed)) mcf5272_uart_t;

// ---------------------------------------------------------------------------

// SDRAM controller
typedef struct
{

    // Gap
    cyg_uint8   _res1[2];

    // SDRAM configuration register
    cyg_uint16  sdcr;

    // Gap
    cyg_uint8   _res2[2];

    // SDRAM timing register
    cyg_uint16  sdtr;

    // Gap
    cyg_uint8   _res3[120];

} __attribute__ ((aligned (4), packed)) mcf5272_sim_sdramctrl_t;

// SDRAM controller related macros

#define MCF5272_SDRAMC_SDCCR_MCAS_A7    (0x0 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A8    (0x1 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A9    (0x2 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A10   (0x3 << 13)
#define MCF5272_SDRAMC_SDCCR_BALOC_A19  (0x0 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A20  (0x1 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A21  (0x2 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A22  (0x3 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A23  (0x4 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A24  (0x5 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A25  (0x6 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A26  (0x7 << 8)
#define MCF5272_SDRAMC_SDCCR_GSL        (0x00000080)
#define MCF5272_SDRAMC_SDCCR_REG        (0x00000010)
#define MCF5272_SDRAMC_SDCCR_INV        (0x00000008)
#define MCF5272_SDRAMC_SDCCR_SLEEP      (0x00000004)
#define MCF5272_SDRAMC_SDCCR_ACT        (0x00000002)
#define MCF5272_SDRAMC_SDCCR_INIT       (0x00000001)

#define MCF5272_SDRAMC_SDCTR_RTP_66MHz  (0x3D << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_48MHz  (0x2B << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_33MHz  (0x1D << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_25MHz  (0x16 << 10)
#define MCF5272_SDRAMC_SDCTR_RC(x)      ((x & 0x3) << 8)
#define MCF5272_SDRAMC_SDCTR_RP(x)      ((x & 0x3) << 4)
#define MCF5272_SDRAMC_SDCTR_RCD(x)     ((x & 0x3) << 2)
#define MCF5272_SDRAMC_SDCTR_CLT_2      (0x00000001)
#define MCF5272_SDRAMC_SDCTR_CLT_3      (0x00000002)
#define MCF5272_SDRAMC_SDCTR_CLT_4      (0x00000003)

// ---------------------------------------------------------------------------

// Timer module
typedef struct
{

    // Timer mode register
    cyg_uint16 tmr;

    // Gap
    cyg_uint16 _res1;

    // Timer reference register
    cyg_uint16 trr;

    // Gap
    cyg_uint16 _res2;

    // Timer capture register
    cyg_uint16 tcap;

    // Gap
    cyg_uint16 _res3;

    // Timer counter register
    cyg_uint16 tcn;

    // Gap
    cyg_uint16 _res4;

    // Timer event register
    cyg_uint16 ter;

    // Gap
    cyg_uint16 _res5;

    // Gap
    cyg_uint32 _res6[3];

} __attribute__ ((aligned (4), packed)) mcf5272_timer_t;

// Related macros

#define MCF5272_TIMER_TMR_PS            (0xFF00)
#define MCF5272_TIMER_TMR_PS_BIT        (8)
#define MCF5272_TIMER_TMR_CE            (0x00C0)
#define MCF5272_TIMER_TMR_CE_BIT        (6)
#define MCF5272_TIMER_TMR_OM            (0x0020)
#define MCF5272_TIMER_TMR_OM_BIT        (5)
#define MCF5272_TIMER_TMR_ORI           (0x0010)
#define MCF5272_TIMER_TMR_ORI_BIT       (4)
#define MCF5272_TIMER_TMR_FRR           (0x0008)
#define MCF5272_TIMER_TMR_FRR_BIT       (3)
#define MCF5272_TIMER_TMR_CLK           (0x0006)
#define MCF5272_TIMER_TMR_CLK_BIT       (1)
#define MCF5272_TIMER_TMR_RST           (0x0001)
#define MCF5272_TIMER_TMR_RST_BIT       (0)
#define MCF5272_TIMER_TER_REF           (0x0002)
#define MCF5272_TIMER_TER_REF_BIT       (1)
#define MCF5272_TIMER_TER_CAP           (0x0001)
#define MCF5272_TIMER_TER_CAP_BIT       (0)

// ---------------------------------------------------------------------------

// Watchdog timer
typedef struct
{

    // Watchdog reset reference register
    cyg_uint16 wrrr;

    // Gap
    cyg_uint16 _res1;

    // Watchdog interrupt reference register
    cyg_uint16 wirr;

    // Gap
    cyg_uint16 _res2;

    // Watchdog counter register
    cyg_uint16 wcr;

    // Gap
    cyg_uint16 _res3;

    // Watchdog event register
    cyg_uint16 wer;

    // Gap
    cyg_uint16 _res4;

    // Gap
    cyg_uint32 _res5[28];

} __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t;

// ---------------------------------------------------------------------------

// Fast Ethernet Controller module
typedef struct
{

    // Ethernet control register
    cyg_uint32 ecr;

    // Ethernet interrupt event register
    cyg_uint32 eir;

    // Ethernet interrupt mask register
    cyg_uint32 eimr;

    // Interrupt vector status register
    cyg_uint32 ivsr;
                                        
    // Receive descriptor active register
    cyg_uint32 rdar;
                                        
    // Transmit descriptor active register
    cyg_uint32 tdar;
                                        
    // Gap
    cyg_uint8 _res2[0x0880 - 0x0858];

    // MII management frame register
    cyg_uint32 mmfr;

    // MII speed control register
    cyg_uint32 mscr;

    // Gap
    cyg_uint8 _res3[0x08cc - 0x0888];

    // FIFO receive bound register
    cyg_uint32 frbr;

    // FIFO receive start register
    cyg_uint32 frsr;

    // Gap
    cyg_uint8 _res4[0x08e4 - 0x08d4];

    // Transmit FIFO watermark
    cyg_uint32 tfwr;

    // Gap
    cyg_uint8 _res5[0x08ec - 0x08e8];

    // Transmit FIFO start register
    cyg_uint32 tfsr;

    // Gap
    cyg_uint8 _res6[0x0944 - 0x08f0];

    // Receive control register
    cyg_uint32 rcr;

    // Maximum frame length register
    cyg_uint32 mflr;

    // Gap
    cyg_uint8 _res7[0x0984 - 0x094c];

    // Transmit control register
    cyg_uint32 tcr;

    // Gap
    cyg_uint8 _res8[0x0c00 - 0x0988];

    // RAM perfect match address low register
    cyg_uint32 malr;

    // RAM perfect match address high register
    cyg_uint32 maur;

    // Hash table high register
    cyg_uint32 htur;

    // Hash table low register
    cyg_uint32 htlr;

    // Pointer to receive descriptor ring
    cyg_uint32 erdsr;

    // Pointer to transmit descriptor ring
    cyg_uint32 etdsr;
                                        
    // Maximum receive buffer size
    cyg_uint32 emrbr;

    // Gap
    cyg_uint8 _res9[0x0c40 - 0x0c1c];

    // FIFO RAM space
    cyg_uint8 efifo[0x0e00 - 0x0c40];

    // Gap
    cyg_uint8 _res10[0x1000 - 0x0e00];

} __attribute__ ((aligned (4), packed)) mcf5272_fec_t;

// ---------------------------------------------------------------------------

// On-chip peripherals: this structure defines each register's offset from the
// current value of the MBAR register.
typedef struct
{

    // 0x0000: System Integration Module (SIM) general configuration registers
    mcf5272_sim_cfg_t cfg;

    // 0x0020: SIM interrupt controller registers
    mcf5272_sim_int_t intc;

    // 0x0040: SIM chip-select modules
    mcf5272_sim_cs_t cs[8];             

    // 0x0080: SIM general purpose I/O control registers
    mcf5272_sim_gpio_t gpio;

    // 0x00a0: QSPI module
    // TODO: a specific data structure is needed
    cyg_uint32 qspi[8];

    // 0x00c0: PWM module
    // TODO: a specific data structure is needed
    cyg_uint32 pwm[8];

    // 0x00e0: DMA controller
    // TODO: a specific data structure is needed
    cyg_uint32 dmac[8];

    // 0x0100: UART modules
    mcf5272_uart_t uart[2];

    // 0x0180: SIM SDRAM controller
    mcf5272_sim_sdramctrl_t sdramc;

    // 0x0200: timer module
    mcf5272_timer_t timer[4];

    // 0x0280: SIM watchdog timer module
    mcf5272_sim_wdtmr_t wdtimer;

    // 0x0300: physical layer interface controller
    // TODO: a specific data structure is needed
    cyg_uint32 plic[336];
                                        
    // 0x0840: ethernet module
    mcf5272_fec_t fec;

    // 0x1000: USB module
    // TODO: a specific data structure is needed
    cyg_uint32 usb[512];

} __attribute__ ((aligned (4), packed)) mcf5272_devs_t;

// ---------------------------------------------------------------------------
// End of mcf5272_devs.h
#endif // CYGONCE_MCF5272_DEVS_H