var_cache.h

开放源码实时操作系统源码.

#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H

//=============================================================================
//
//      var_cache.h
//
//      Variant HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2006 eCosCentric Ltd.
//
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
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// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
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// in accordance with section (3) of the GNU General Public License.
//
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// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):     Enrico Piria
// Contributors:
// Date:          2005-25-06
// Purpose:       Definitions specific to the MCF5272 processor cache.
// Usage:         Included via "hal_cache.h". Do not use directly.
//
//####DESCRIPTIONEND####
//========================================================================

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/coldfire_regs.h>

// We currently just enable the instruction cache on startup. There is
// no data cache.

// ----------------------------------------------------------------------------
// Cache dimensions - these vary between the ColdFire sub-models

// Data cache
#define HAL_DCACHE_SIZE                 0       // Size of data cache in bytes

// Size of a data cache line. Leave this value even if there is no data cache
// on 5272, otherwise some tests won't compile.
#define HAL_DCACHE_LINE_SIZE            16

#define HAL_DCACHE_WAYS                 1       // Associativity of the cache

// Instruction cache
#define HAL_ICACHE_SIZE                 1024    // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
#define HAL_ICACHE_WAYS                 1       // Associativity of the cache

#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))

// ----------------------------------------------------------------------------
// Global control of data cache

// Enable the data cache
#define HAL_DCACHE_ENABLE()

// Disable the data cache
#define HAL_DCACHE_DISABLE()

// Invalidate the entire cache
// Note: Any locked lines will not be invalidated.
#define HAL_DCACHE_INVALIDATE_ALL()

// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()

// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_)

// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)

// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )

//#define HAL_DCACHE_WRITETHRU_MODE       0
//#define HAL_DCACHE_WRITEBACK_MODE       1


// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_DCACHE_LOCK(_base_, _size_)

// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK(_base_, _size_)

// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL()

// ----------------------------------------------------------------------------
// Data cache line control

// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )

// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH( _base_ , _size_ )

// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )

// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE( _base_ , _size_ )

// Preread the given range into the cache with the intention of reading
// from it later.
#define HAL_DCACHE_READ_HINT( _base_ , _size_ )

// Preread the given range into the cache with the intention of writing
// to it later.
#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )

// Allocate and zero the cache lines associated with the given range.
#define HAL_DCACHE_ZERO( _base_ , _size_ )

// ----------------------------------------------------------------------------
// Global control of Instruction cache

// Enable the instruction cache
#define HAL_ICACHE_ENABLE() CYGARC_MOVEC((CYG_WORD32)0x80000102, CYGARC_REG_CACR)

// Disable the instruction cache
#define HAL_ICACHE_DISABLE() CYGARC_MOVEC((CYG_WORD32)0x00000102, CYGARC_REG_CACR)

// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() CYGARC_MOVEC((CYG_WORD32)0x81000102, CYGARC_REG_CACR)

// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC() CYGARC_MOVEC((CYG_WORD32)0x81000102, CYGARC_REG_CACR)

// Query the state of the instruction cache
//#define HAL_ICACHE_IS_ENABLED(_state_)

// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)


// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK(_base_, _size_)

// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK(_base_, _size_)

// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL()

// ----------------------------------------------------------------------------
// Instruction cache line control

// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )

// ---------------------------------------------------------------------------
// End of var_cache.h
#endif // ifndef CYGONCE_VAR_CACHE_H