📄 mcf5272_sim.h
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#ifndef MCF5272_SIM_H
#define MCF5272_SIM_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
/*
Defines for the mcf5272 System Integration Module (SIM)
*/
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
/* General configuration registers. */
typedef struct mcf5272_sim_cfg_t
{
u32_t mbar; /* Module base address register */
/* (MBAR), after initialization */
u16_t scr; /* System configuration register */
u16_t spr; /* System protection register */
u32_t pmr; /* Power management register */
u16_t res1;
u16_t alpr; /* Active low power register */
u32_t dir; /* Device identification register */
u32_t res2[3];
} __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t;
/* Interrupt controller registers. */
typedef struct mcf5272_sim_int_t
{
u32_t icr[4]; /* Interrupt control register 1-4 */
u32_t isr; /* Interrupt source register */
u32_t pitr; /* Programmable interrupt */
/* transition register */
u32_t piwr; /* Programmable interrupt wakeup */
/* register */
u8_t res1[3];
u8_t ipvr; /* Programmable interrupt vector */
/* register */
} __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t;
/* Chip Select Module */
typedef struct mcf5272_sim_cs_t
{
u32_t csbr; /* CS base register. */
u32_t csor; /* CS option register. */
} __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t;
/* General Purpose I/O Module */
typedef struct mcf5272_sim_gpio_t
{
/* Use the following labels to initialize the bits in the data */
/* direction registers. Setting the bit to zero indicates that this */
/* pin is an input, one indicates an input. */
#define MCF5272_GPIO_DDR_IN (0)
#define MCF5272_GPIO_DDR_OUT (1)
u32_t pacnt; /* Port A control register. */
u16_t paddr; /* Port A data direction */
/* register. */
u16_t padat; /* Port A data register. */
u32_t pbcnt; /* Port B control register. */
/* Set these bits in the port B control register to enable the */
/* Ethernet, UART0, and data transfer acknowledge pins. */
#define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000)
#define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000)
#define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000)
#define MCF5272_GPIO_PBCNT_TA_EN (0x00000400)
#define MCF5272_GPIO_PBCNT_TA_DE (0x00000000)
#define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00)
#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155)
#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000)
#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF)
u16_t pbddr; /* Port B data direction */
/* register. */
u16_t pbdat; /* Port B data register. */
u32_t res1;
u16_t pcddr; /* Port C data direction */
/* register. */
u16_t pcdat; /* Port C data register. */
u32_t pdcnt; /* Port D control register. */
/* Set these bits in the port D control register to enable the UART1 */
/* and interrupt 4 pins. */
#define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00)
#define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000)
#define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00)
#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA)
#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000)
#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF)
u16_t res2;
u16_t res3;
} __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t;
/* UART Module */
typedef struct mcf5272_sim_uart_t
{
u8_t umr; /* UART mode register. */
u8_t res1[3];
#define MCF5272_UART_UMR_8BNP (0x13) /* Write this value to umr1 to */
/* program the device for 8 bits */
/* and no parity. */
#define MCF5272_UART_UMR_1S (0x07) /* Write this value to umr2 to */
/* program the device for 1 stop */
/* bit. */
u8_t usr_ucsr; /* UART status register (R) and */
u8_t res2[3]; /* UART clock-select register (W). */
#define MCF5272_UART_USR_RRDY (1<<0) /* Bit 0 of the device status */
/* register is set when the receive */
/* data register contains data. If */
/* the data is not removed from the */
/* holding register, additional */
/* data will be placed in the FIFO */
/* until the FIFO is overrun. */
#define MCF5272_UART_USR_FFUL (1<<1) /* Bit 1 of the device status */
/* register is set when the receive */
/* data FIFO is full. If a */
/* character is not removed before */
/* the next character is received, */
/* overrun will occur. */
#define MCF5272_UART_USR_TXRDY (1<<2) /* Bit 2 of the device status */
/* register is set when the */
/* transmit data holding register */
/* is empty. Note that this is */
/* different than the FIFO being */
/* empty as the FIFO may still */
/* contain characters even if the */
/* holding register is empty. */
#define MCF5272_UART_USR_TXEMP (1<<3) /* Bit 3 of the device status */
/* register is set when the */
/* transmit data FIFO is empty. */
#define MCF5272_UART_USR_OE (1<<4) /* Bit 4 of the device status */
/* register is set when an overrun */
/* error has occurred. */
#define MCF5272_UART_USR_PE (1<<5) /* Bit 5 of the device status */
/* register is set when a parity */
/* error has occurred. */
#define MCF5272_UART_USR_FE (1<<6) /* Bit 6 of the device status */
/* register is set when a framing */
/* error has occurred. */
#define MCF5272_UART_USR_RB (1<<7) /* Bit 7 of the device status */
/* register is set when a change in */
/* break status has occurred on the */
/* port. */
#define MCF5272_UART_UCSR_CLKIN (0xDD) /* Writing this value to the ucsr */
/* selects CLKIN/16 as the UART's */
/* clock source. */
u8_t ucr; /* UART command register (W). */
u8_t res3[3];
#define MCF5272_UART_UCR_RMR (0x01<<4) /* Write this value to ucr to */
/* reset the mode register to umr1. */
#define MCF5272_UART_UCR_RRX (0x02<<4) /* Write this value to ucr to */
/* reset the receiver. */
#define MCF5272_UART_UCR_RTX (0x03<<4) /* Write this value to ucr to */
/* reset the transmitter. */
#define MCF5272_UART_UCR_RES (0x04<<4) /* Write this value to ucr to */
/* reset the error status. */
#define MCF5272_UART_UCR_RBC (0x05<<4) /* Write this value to ucr to */
/* reset the break change */
/* interrupt. */
#define MCF5272_UART_UCR_TXEN (1<<2) /* Write this value to ucr to */
/* enable the transmitter. */
#define MCF5272_UART_UCR_TXDE (1<<3) /* Write this value to ucr to */
/* disable the transmitter. */
#define MCF5272_UART_UCR_RXEN (1<<0) /* Write this value to ucr to */
/* enable the receiver. */
#define MCF5272_UART_UCR_RXDE (1<<1) /* Write this value to ucr to */
/* disable the receiver. */
/* Write this value to the ucr to */
/* enablt the transmitter and */
/* receiver. */
#define MCF5272_UART_UCR_TXRXEN \
(MCF5272_UART_UCR_TXEN | \
MCF5272_UART_UCR_RXEN)
u8_t urb_utb; /* UART receiver buffers (R) and */
u8_t res4[3]; /* UART transmitter buffers (W). */
u8_t uipcr_uacr; /* UART input port change */
u8_t res5[3]; /* register (R) and UART auxiliary */
/* control register (W). */
u8_t uisr_uimr; /* UART interrupt status register */
u8_t res6[3]; /* (R) and UART interrupt mask */
/* register (W). */
u8_t udu; /* UART divider upper register */
u8_t res7[3]; /* (W). */
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