vads.s

开放源码实时操作系统源码.

   addis    r3,0,0x0450     # R3 holds the value temporarily
   ori      r3,r3,0x1801

   #-------------------------------------------------------------------------
   # Option Register 1 (OR1) for GPCM use: further BCSR definitions
   #
   # AM (Address Mask) = 0xFFFF +1b = We have masked the upper 17 bits which 
   #                                  which defines a 32 Kbyte memory block.
   #
   # Bits 17-19 Reserved - set to 000.
   #
   # CSNT (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally.
   #
   # ACS (Address To Chip-Select Setup) = 00 = CS/ is output at the same 
   #                                           time as the addr lines.
   #
   # Bit 23 Reserved - set to 0.
   #
   # SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state
   #
   # SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated 
   #                                            internally by the memory 
   #                                            controller unless GTA/ is 
   #                                            asserted earlier externally.
   #
   # TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM.
   #
   # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is 
   #                                                  generated by the memory
   #                                                  controller
   #
   # Bit 31 Reserved - set to 0.
   #-------------------------------------------------------------------------

   addis    r5,0,0xFFFF     # R5 holds the value temporarily
   ori      r5,r5,0x8010

   #------------------
   # Write the values
   #------------------

   stw        r5,CYGARC_REG_IMM_OR1(r4)
   stw        r3,CYGARC_REG_IMM_BR1(r4)


   bclr  20,0    # jump unconditionally to effective address in Link
                 # register



#########################################################################
# Function: init_60x_sdram
#
# Description: This function programs the 16 Mbyte SDRAM DIMM on the VADS 
#              board. This memory functions as the RAM for the 603 core and
#              is connected to the 60x bus. Base and Option Register 2 are 
#              used as well as the SDRAM Machine #1 and Chip Select #2.
#
#  History:
#
#  Jan /9/99    jay      Initial Release
#
#########################################################################        

init_60x_sdram:


   ##################
   # Program Refresh
   ##################


   #-------------------------------------------------------------------------
   # Program the 60x Bus Assigned SDRAM Refresh Timer (PSRT).
   #-------------------------------------------------------------------------

   addi     r5,0,0x0010      # load 0x10 or 16 
   stb      r5,CYGARC_REG_IMM_PSRT(r4)      # store byte - bits[24-31]


   #########################
   # Program Bank Registers
   #########################


   #-------------------------------------------------------------------------
   # Base Register 2 (BR2): Bank 2 is assigned to the 16 Mbyte 60x SDRAM DIMM
   #                        that resides on the MPC8260 VADS board. The 
   #                        particulars are defined here. 
   #
   # - BA (Base Address) = 0x0000+0b for a total of 17 address bits. This 
   #                       value represents the upper 17 bits of the base 
   #                       address.
   #
   # - Bits 17-18 reserved. = 00 = cleared to 0.
   #
   # - PS (Port Size) = 00b = 64 bit port size
   #
   # - DECC (Data Error Correction and Checking) = 00 = Data errors checking
   #                                                    Disabled.
   #
   # - WP (Write Protect) = 0 = both read and write accesses are allowed
   #
   # - MS (Machine Select) = 010 = SDRAM Machine for 60x bus Selected
   #
   # - EMEMC (External Memory Controller Enable) = 0 = 
   #
   #    Accesses are handled by the memory controller according to MSEL.
   #
   # - ATOM (Atomic Operation) = 00 = The address space controlled by the 
   #                                  memory controller bank is not used for
   #                                  atomic operations.
   #
   # - DR (Delayed Read) = 0 = Normal operation.
   #
   # - V (Valid Bit) =  1 = Valid bit set
   #-------------------------------------------------------------------------

   addis    r3,0,0x0000     # R3 holds the value temporarily
   ori      r3,r3,0x0041

   #-------------------------------------------------------------------------
   # Option Register 2 (OR2) for SDRAM Machine use: further SDRAM definitions
   #
   # - USDAM (Upper SDRAM Address Mask) = 11111b = 
   #
   #    We have masked all 5 bits which defines a maximum 128 Mbyte block.
   #    Note that since the maximum SDRAM block size is 128 Mbyte, this field
   #    should always be 11111b.
   #
   # - SDAM (SDRAM Address Mask) = 1110000b = 16 Mbyte block.
   #
   # - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size.
   #
   # - BPD (Banks Per Device) = 00 = 2 internal banks per device.
   #
   # - ROWST (Row Start Address Bit) = 011 = A9 being the row start address 
   #                                         bit.
   #
   # - Bit 22 Reserved - set to 0.
   #
   # - NUMR (Number of Row Address Lines) = 010 = 11 row address lines.
   #
   # - PMSEL (Page Mode Select) = 1 = Reserved
   #
   # - IBID (Internal bank interleaving within same device disable) = 0 =
   # 
   #    Bank interleaving allowed.
   #
   # - AACKR (AACK/ release) = 0 = Normal operation.
   #
   # - Bits 29-31 Reserved - set to 0.
   #-------------------------------------------------------------------------

#define nCYGHWR_HAL_POWERPC_VADS_64MB_DIMM
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
   addis    r5,0,0xFC00     # R5 holds the value temporarily
   ori      r5,r5,0x28E0
#else
   addis    r5,0,0xFF00     # R5 holds the value temporarily
   ori      r5,r5,0x0CA0
#endif

   #------------------
   # Write the values
   #------------------

   stw        r5,CYGARC_REG_IMM_OR2(r4)
   stw        r3,CYGARC_REG_IMM_BR2(r4)


   ###########################################
   # Perform Initialization sequence to SDRAM
   ###########################################

   #-------------------------------------------------------------------------
   # Program the PowerPC SDRAM Mode Registr (PSDMR). This register is used
   # to configure operations pertaining to SDRAM. Program the PSDMR, turning 
   # off refresh services and changing the SDRAM operation to "Precharge all
   # banks". Then do a single write to an arbitrary location. Writing 0xFF 
   # to address 0 will do the trick.
   #
   # - Bit 0 is reserved. Set to 0.
   #
   # - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit 
   #                               will be set later in this function as a 
   #                               last step.
   # 
   # - OP (SDRAM Operation) = 000 = Precharge all banks.
   #
   # - SDAM (Address Multiplex Size = 001 = 
   #
   #   Coming up the value for this field is one of the most confusing
   #   and non-intuitive steps in the SDRAM programming process. This is how
   #   it works... The SDRAM device is a 16 Mbit DIMM that has a data width 
   #   of 64 bits or 8 bytes. The bank size is 64 bits so the SDRAM will 
   #   ignore the least significant 3 bits. Given this information and 
   #   knowing that the number of row address lines is 11 and the column 
   #   addresses is 9 and also knowing that the row addresses must be 
   #   multiplexed, write out the following:
   #
   #   addresses ignored by SDRAM : A29 A30 A31
   #
   #   column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28
   #
   #   row addresses:   A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
   #
   #   When the memory controller multiplexes the addresses it puts the 
   #   column addresses out on the actual physical pins that matches its
   #   corresponding effective address bits.
   #
   #   According to the SDRAM Address Multiplexing table in the memory 
   #   controller section of the manual, SDAM selection of 001 fits the 
   #   address layout given above. Because its the row that is multiplexed on
   #   designated column address pins, the row addresses are put out on the
   #   following column pins:
   #
   #   column ---------------------->  A20 A21 A22 A23 A24 A25 A26 A27 A28
   #                                    |   |   |   |   |   |   |   |   |
   #   row address -----------> A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
   #   on corresponding
   #   column pins.
   #
   #   Column pins A19, A18, and A17 were not connected to the DIMM device so
   #   A9 and A10 as well as the bank select address which is A8 are put out 
   #   on their respective pins because it was decided that these address 
   #   pins would be directly connected to the DIMM. That is, A10 of the real
   #   address is put out on the A10 pin, A9 on the A9 pin, etc.
   #
   #   As a final note on this subject, the row address is output on the 
   #   address bus first on the actual column address pins according to the 
   #   multiplexing scheme in the SDRAM address multiplexing table, then the 
   #   column address follows which makes up the most significant part of the
   #   real address which is connected to the memory device. 
   #
   #   Any entries in the multiplexing table that show a "-" means nothing is
   #   multiplexed on the physical pins shown on the top row of the table
   #   and therefore any part of the row address will also show up on its 
   #   respective physical pin if this pin is not used for multiplexing. For 
   #   example, for a SDAM of 001, the multiplexing table shows that A13 
   #   through A0 are not multiplexed because they have "-" in their 
   #   respective boxes. This means that A13 through A5 of the real address
   #   will show up multiplexed on address pins A22 through A14 and A13 
   #   through A0 of the real address will also show up on their actual 
   #   respective physical pins.
   #
   # - BSMA (Bank Select Multiplexed Address line) = 011 = A15-A17
   #
   #    BSMA determines how BNKSEL[0:2] will operate. This SDRAM has only 2 
   #    banks, so only BANKSEL2 is of concern because its the least 
   #    significant bit. BANKSEL2 should be programmed to operate as physical 
   #    pin A17. Because we are multiplexing 9 column addresses, it will 
   #    actually behave as A8. 
   #
   # - SDA10 ("A10 Control") = 011 = 
   #
   #    A9 is the address pin used for the activate command. The A10/AP pin
   #    the SDRAM needs to act as a command line during on phase of the 
   #    access and as an address line in the other phase. The SDA10 pin on 
   #    MPC8260 takes care of this function. Instead of connecting the 
   #    A10/AP pin to A9 on the address bus, connect it to SDA10 and program
   #    SDA10 to function as A9.
   #
   # - RFRC (ReFresh ReCovery) = 101 = 
   #
   #   Once a  refresh request is granted, the memory controller begins 
   #   issuing auto-refresh commands to each device associated with the 
   #   refresh timer in one clock intervals. After the last REFRESH 
   #   command is issued, the memory controller waits for 7 clocks before 
   #   the ACTIVATE command and before normal read/write operations can 
   #   resume.
   #
   # - PRETOACT (PREcharge TO ACTivate interval) = 011 = 
   #
   #   Wait 3 clock cycles before an activate command. This parameter is
   #   determined by the requirements of the SDRAM at a particular clock 
   #   speed.
   #
   # - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles.
   # 
   # - BL (Burst Length) = 0 = SDRAM burst length is 4. This is programmed 
   #                          into the SDRAM via the MRS commmand.
   #
   # - LDOTOPRE (Last Data Out TO PREcharge) = 01 = 
   #
   #   The delay required from the last data out to precharge state is 1 clock
   #   cycle. This parameter is determined by the requirements of the SDRAM at
   #   a particular clock speed.
   #                               
   # - WRC (Write Recovery Time) = 01 = 
   #
   #   Time needed to elapse before another operation is 1 clock cycle. This 
   #   parameter is determined by the requirements of the SDRAM at a 
   #   particular clock speed.
   #
   # - EAMUX (External Address MUltipleXing) = 0 No external address
   #                                             multiplexing.
   #
   # - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control
   #                                       lines.
   #
   # - CL (CAS Latency) = 10 = 
   #
   #    CAS latency is 2. Two cycles after column address is registered, data
   #    is valid. This parameter is determined by the requirements of the 
   #    SDRAM at a particular clock speed.
   #
   #-------------------------------------------------------------------------

#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
   addis    r3,0,0x294E
   ori      r3,r3,0xB452
#else
   addis    r3,0,0x296E
   ori      r3,r3,0xB452
#endif
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)
   addis    r0,0,0

   addi     r3,0,0x00FF      # Load 0x000000FF into r3
   stb      r3,0(r0)         # Write 0xFF to address 0 - bits [24-31]
   

   #-------------------------------------------------------------------------
   # Program the PSDMR keeping refresh services off and changing the
   # SDRAM operation to "CBR Refresh". This step is responsible for issuing
   # a minimum of 8 auto-refresh commands. This is done by the SDRAM machine
   # by issuing the CBR Refresh command by programming the OP field of the 
   # PSDMR register and writing 0xFF 8 times to an arbitrary address.
   #-------------------------------------------------------------------------
   
#ifdef CYGHWR_HAL_POWERPC_VADS_64MB_DIMM
   addis    r3,0,0x094E
   ori      r3,r3,0xB452
#else
   addis    r3,0,0x096E
   ori      r3,r3,0xB452
#endif
   stw      r3,CYGARC_REG_IMM_PSDMR(r4)

   #------------------------------------------
   # Loop 8 times, writing 0xFF to address 0
   #------------------------------------------

   addi  r6,0,0x0008
   mtspr CYGARC_REG_CTR,r6             # Load CTR with 8. The CTR special purpose
                            # is spr 9

   addi  r3,0,0x00FF      # Load 0x000000FF into r3