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# MODCK2|AP(2)|TC(1) = BNKSEL(1)
# MODCK3|AP(3)|TC(2) = BNKSEL(2)
# IRQ7/|APE/|INT_OUT/ = IRQ7/+INT_OUT/
# CS11/|AP(0) = CS11/
#
# - CS10PC (Chip Select 10-pin Configuration) = 00 =
#
# CS10/|BCTL1/|DBG_DIS/ = CS10/
#
# - BCTLC (Buffer Control Configuration) = 00 =
#
# BCTL0 pin is used as W|R/ control. BCTL1 is used as OE/ control if
# BCTL1 was connected to its alternate pin.
#
# - MMR (Mask Masters Requests) = 00 = No masking on bus request lines.
#
# - LPBSE (Local Bus Parity Byte Select Enable) = 0
#
# Parity byte select is disabled.
#
# Bits 19-31 are reserved and set to 0.
#
#------------------------------------------------------------------------
#--------------------------------------------------------------------------
# Program the 60x Bus Transfer Error Status and Control Register 1. The
# details are as follows:
#
# - DMD (Data Errors Disable) = 1 =
#
# Disable all data errors on the 60x bus. Also parity single and double
# ECC error.
#
# - All other bits are either status or reserved bits. All reserved bits
# should be set to 0.
#--------------------------------------------------------------------------
addis r3,0,0x0000
ori r3,r3,0x4000
stw r3,CYGARC_REG_IMM_TESCR1(r4)
#--------------------------------------------------------------------------
# Program the Local Bus Transfer Error Status and Control Register 1. The
# details are as follows:
#
# - DMD (Data Errors Disable) = 1 =
#
# Disable parity errors on the Local bus.
#
# - All other bits are either status or reserved bits. All reserved bits
# should be set to 0.
#--------------------------------------------------------------------------
addis r3,0,0x0000
ori r3,r3,0x4000
stw r3,CYGARC_REG_IMM_LTESCR1(r4)
#-------------------------------------------------------------------------
# First, program the Memory Periodic Timer Prescaler Register (MPTPR).
# Finding the value to this ties in with the desired SDRAM Refresh
# Timer (PSRT) value and the required Refresh Command interval for
# refreshing each row. The Refresh Command interval is found by
# determining the number of rows on the SDRAM device. In this case
# its 2048. The "total time between refresh" value in the AC characteristic
# section of the data sheet is 32.8 msec. This value is divided by the
# number of rows to give the number of Refresh commands that needs to be
# sent in a 32.8 msec interval. This value is 32.8 Msec/2048 = 16.02 usec.
# Due to probable contention from time to time with other memory
# controller bus requests, lets make the refresh command interval to be
# around 15.5 usec.
#
# Now let us divide the input VADs system clock by 64 (somewhat arbitrary).
# If this is our prescaler value then the input frequency to the Refresh
# timer is 1.031 Mhz. Using the formula:
#
# Timer Period = PSRT
# ----
# F(MPTC)
#
# - Where F(MPTC) is the output from the MPT Prescaler block
# or 66 Mhz/64 = 1.031 Mhz.
#
# - Timer Period = 15.5 usec
#
# The PSRT value would be approximately 16.
#
# The clock distribution block diagram looks like this:
#
# ---------- ------------- ----------- -------------
# | Clock | | MPT | | SDRAM | | Refresh |
# | Gen. |-----| Prescaler |---------| Refresh |----| Command |
# | 66 Mhz | ------------- | Timer | | Logic in |
# | on Vads | ----------- | Mem.Cont. |
# | Board | -------------
# -----------
#
#-------------------------------------------------------------------------
addi r5,0,0x4000 # load 0x40 or 64 into the PTP field of MPTPR
sth r5,CYGARC_REG_IMM_MPTPR(r4) # store half word - bits[16-31]
#-----------------------
# return from init_siu
#-----------------------
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_memc
#
# Description:
#
# The following registers directly control the memory controllers
# operation:
#
# BR0-BR11 - Base Register Banks 0-11
# OR0-OR11 - Option Register Banks 0-11
# PSDMR - 60x bus SDRAM machine mode register
# LSDMR - Local bus SDRAM machine mode register
# MAMR - UPMA mode register
# MBMR - UPMB mode register
# MCMR - UPMC mode register
# MDR - Memory data register
# MAR - Memory address register
# MPTPR - Memory periodic timer pre-scaler register
# PURT - 60x bus assigned UPM refresh timer
# PSRT - 60x bus assigned SDRAM refresh timer
# LURT - Local Bus assigned UPM refresh timer
# LSRT - Local Bus assigned SDRAM refresh timer
#
# This example will program the following registers. The rest will remain at
# their default values.
#
# BR0 - Base Register for Flash Memory
# OR0 - Option Register for Flash Memory
# BR1 - Base Register for BCSR (Board Control and Status Registers)
# OR1 - Option Register for BCSR
# BR2 - Base Register for 60x SDRAM
# OR2 - Option Register for 60x SDRAM
# BR3 - Base Register for 60x Local Bus SDRAM
# OR3 - Option Register for 60x Local Bus SDRAM
# PSDMR - 60x bus SDRAM machine mode register
# LSDMR - Local bus SDRAM machine mode register
# MPTPR - Memory periodic timer pre-scaler register
# PSRT - 60x bus assigned SDRAM refresh timer
# LSRT - Local Bus assigned SDRAM refresh timer
#
#
# History:
#
#########################################################################
init_memc:
mfspr r30,CYGARC_REG_LR # Save the Link Register value. The link registers
# value will be restored so that this function
# can return to the calling address.
bl init_flash # 8 Mbyte of flash memory
bl init_bcsr # Board Control and Status Registers
bl init_local_sdram # Local Bus SDRAM
bl init_60x_sdram # Main 60x Bus SDRAM
#-----------------------
# return from init_memc
#-----------------------
mtspr CYGARC_REG_LR,r30 # restore original Link Register value
bclr 20,0 # jump unconditionally to effective address in Link
# register
############################################################################
# Function: init_flash
#
# Description: This function programs Base Register 0 and Option Register 0
# designating bank 0 for the 8Mbyte flash SIMM on the VADS
# board. Programming these two registers describes how the
# MPC8260 will inter-operate with this memory space and thus
# this memory device.
#
# History:
#
############################################################################
init_flash:
#-------------------------------------------------------------------------
# Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
# flash that resides on the MPC8260 VADS board.
# The particulars are defined here.
#
# BA (Base Address) = 0xFF80+0b for a total of 17 address bits. This value
# represents the upper 17 bits of the base address.
#
# Bits 17-18 reserved. = 00
#
# PS (Port Size) = 11b = 32 bit port size
#
# DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# WP (Write Protect) = 0 = both read and write accesses are allowed
#
# MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
# for 60x bus Selected
#
# EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
# the memory controller
# according to MSEL.
#
# ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# DR (Delayed Read) = 0 = Normal operation.
#
# V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
#define nPFHACK
#ifdef PF_HACK // move Flash from 0xFF800000 to 0xFE000000
addis r3,0,0xFE00 # R3 holds the value temporarily
#else
addis r3,0,0xFF80 # R3 holds the value temporarily
#endif
ori r3,r3,0x1801
#-------------------------------------------------------------------------
# Option Register 0 (OR0) for GPCM use: further flash definitions
#
# AM (Address Mask) = 0xFF80+0b = We have masked the upper 9 bits which
# defines a 8 Mbyte memory block.
#
# Bits 17-19 Reserved - set to 000.
#
# CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter
# of a clock early.
#
# ACS (Address To Chip-Select Setup) = 00 = CS/ is output the same time as
# the addr lines.
#
# Bit 23 Reserved - set to 0.
#
# SCY (Cycle Length In Clocks) = 0011 = Add a 3 clock cycle wait state
#
# SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated
# internally by the memory
# controller unless GTA/ is
# asserted earlier externally.
#
# TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM.
#
# EHTR (Extended Hold Time On Read Accesses) = 1 =
#
# Extended hold time is generated by the memory controller. An idle
# clock cycle is inserted between a read access from the current bank
# and any write or read access to a different bank.
#
# Bit 31 Reserved - set to 0.
#-------------------------------------------------------------------------
#ifdef PF_HACK // move Flash from 0xFF800000 to 0xFE000000
addis r5,0,0xFE00 # R5 holds the value temporarily
#else
addis r5,0,0xFF80 # R5 holds the value temporarily
#endif
ori r5,r5,0x0836
#------------------------------------------------------------------------
# It is important to note the order in which OR0 and BR0 are programmed.
# When coming out of reset and CS0 is the global chip select, OR0 MUST be
# programmed AFTER BR0. In all other cases BRx would be programmed after
# ORx.
#------------------------------------------------------------------------
#------------------
# Write the values
#------------------
stw r3,CYGARC_REG_IMM_BR0(r4)
stw r5,CYGARC_REG_IMM_OR0(r4)
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_bcsr
#
# Description: This function programs Base Register 1 and Option Register 1
# designating bank 1 for BCSR0, BCSR1, and BCSR2 on the VADS
# board. BCSR stands for Board Control and Status Register.
# This space is treated as general I/O. Programming the
# following 2 registers describes how the MPC8260 will inter-
# operate with this memory space.
#
# History:
#
# Jan 9/99 jay
#
#########################################################################
init_bcsr:
#-------------------------------------------------------------------------
# Base Register 1 (BR1): Bank 1 is assigned to the Board Control and
# Status Registers (BCSRs). There are 3
# that resides on the MPC8260 VADS board.
# The particulars are defined here.
#
# BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value
# represents the upper 17 bits of the base address.
#
# Bits 17-18 reserved. = 00
#
# PS (Port Size) = 11b = 32 bit port size
#
# DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# WP (Write Protect) = 0 = both read and write accesses are allowed
#
# MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
# for 60x bus Selected
#
# EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
# the memory controller
# according to MSEL.
#
# ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# DR (Delayed Read) = 0 = Normal operation.
#
# V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
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