📄 ppc8xx.h
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volatile unsigned short timer_tcr4; /* timer 4 capture reg */
volatile unsigned short timer_tcn3; /* timer 3 counter reg */
volatile unsigned short timer_tcn4; /* timer 4 counter reg */
volatile unsigned short timer_ter1; /* timer 1 event reg */
volatile unsigned short timer_ter2; /* timer 2 event reg */
volatile unsigned short timer_ter3; /* timer 3 event reg */
volatile unsigned short timer_ter4; /* timer 4 event reg */
volatile unsigned char RSRVD23[0x8];
/* CP */
volatile unsigned short cp_cr; /* command register */
volatile unsigned char RSRVD24[0x2];
volatile unsigned short cp_rccr; /* main configuration reg */
volatile unsigned char RSRVD25;
volatile unsigned char cp_resv1; /* RSRVD reg */
volatile unsigned long cp_resv2; /* RSRVD reg */
volatile unsigned short cp_rctr1; /* ram break register 1 */
volatile unsigned short cp_rctr2; /* ram break register 2 */
volatile unsigned short cp_rctr3; /* ram break register 3 */
volatile unsigned short cp_rctr4; /* ram break register 4 */
volatile unsigned char RSRVD26[0x2];
volatile unsigned short cp_rter; /* RISC timers event reg */
volatile unsigned char RSRVD27[0x2];
volatile unsigned short cp_rtmr; /* RISC timers mask reg */
volatile unsigned char RSRVD28[0x14];
/* BRG */
volatile unsigned long brgc1; /* BRG1 configuration reg */
volatile unsigned long brgc2; /* BRG2 configuration reg */
volatile unsigned long brgc3; /* BRG3 configuration reg */
volatile unsigned long brgc4; /* BRG4 configuration reg */
/* SCC registers */
struct scc_regs {
volatile unsigned long scc_gsmr_l; /* SCC Gen mode (LOW) */
volatile unsigned long scc_gsmr_h; /* SCC Gen mode (HIGH) */
volatile unsigned short scc_psmr; /* protocol specific mode register */
volatile unsigned char RSRVD29[0x2];
volatile unsigned short scc_todr; /* SCC transmit on demand */
volatile unsigned short scc_dsr; /* SCC data sync reg */
volatile unsigned short scc_scce; /* SCC event reg */
volatile unsigned char RSRVD30[0x2];
volatile unsigned short scc_sccm; /* SCC mask reg */
volatile unsigned char RSRVD31[0x1];
volatile unsigned char scc_sccs; /* SCC status reg */
volatile unsigned char RSRVD32[0x8];
} scc_regs[4];
/* SMC */
struct smc_regs {
volatile unsigned char RSRVD34[0x2];
volatile unsigned short smc_smcmr; /* SMC mode reg */
volatile unsigned char RSRVD35[0x2];
volatile unsigned char smc_smce; /* SMC event reg */
volatile unsigned char RSRVD36[0x3];
volatile unsigned char smc_smcm; /* SMC mask reg */
volatile unsigned char RSRVD37[0x5];
} smc_regs[2];
/* SPI */
volatile unsigned short spi_spmode; /* SPI mode reg */
volatile unsigned char RSRVD38[0x4];
volatile unsigned char spi_spie; /* SPI event reg */
volatile unsigned char RSRVD39[0x3];
volatile unsigned char spi_spim; /* SPI mask reg */
volatile unsigned char RSRVD40[0x2];
volatile unsigned char spi_spcom; /* SPI command reg */
volatile unsigned char RSRVD41[0x4];
/* PIP */
volatile unsigned short pip_pipc; /* pip configuration reg */
volatile unsigned char RSRVD42[0x2];
volatile unsigned short pip_ptpr; /* pip timing parameters reg */
volatile unsigned long pip_pbdir; /* port b data direction reg */
volatile unsigned long pip_pbpar; /* port b pin assignment reg */
volatile unsigned char RSRVD43[0x2];
volatile unsigned short pip_pbodr; /* port b open drain reg */
volatile unsigned long pip_pbdat; /* port b data reg */
volatile unsigned char RSRVD44[0x18];
/* Serial Interface */
volatile unsigned long si_simode; /* SI mode register */
volatile unsigned char si_sigmr; /* SI global mode register */
volatile unsigned char RSRVD45;
volatile unsigned char si_sistr; /* SI status register */
volatile unsigned char si_sicmr; /* SI command register */
volatile unsigned char RSRVD46[0x4];
volatile unsigned long si_sicr; /* SI clock routing */
volatile unsigned long si_sirp; /* SI ram pointers */
volatile unsigned char RSRVD47[0x10c];
volatile unsigned char si_siram[0x200];/* SI routing ram */
volatile unsigned short lcd_lcolr[256]; /* LCD Color RAM -- REV A.x */
volatile unsigned char RSRVD48[0x1000];
/* BASE + 0x2000: user data memory */
volatile unsigned char udata_ucode[0x800]; /* user data bd's Ucode*/
volatile unsigned char bd[0x700]; /* buffer descriptors, data */
volatile unsigned char udata_ext[0x100]; /* extension area for downloaded ucode */
volatile unsigned char RSRVD49[0x0C00];
/* BASE + 0x3c00: PARAMETER RAM */
union {
struct scc_pram {
union {
struct hdlc_pram h;
struct uart_pram u;
struct bisync_pram b;
struct transparent_pram t;
struct async_hdlc_pram a;
unsigned char RSRVD50[0x80];
} pscc; /* scc parameter area (protocol dependent) */
union {
struct {
struct i2c_pram i2c;
unsigned char RSRVD56[0x10];
struct idma_pram idma1;
} i2c_idma;
struct {
struct spi_pram spi;
struct timer_pram timer;
struct idma_pram idma2;
} spi_timer_idma;
struct {
union {
struct smc_uart_pram u;
struct smc_trnsp_pram t;
struct centronics_pram c;
} psmc;
unsigned char modem_param[0x40];
} smc_modem;
struct {
unsigned char RSRVD54[0x40];
struct ucode_pram ucode;
} pucode;
} pothers;
} scc;
struct ethernet_pram enet_scc;
unsigned char pr[0x100];
} pram[4];
} EPPC;
static inline EPPC *eppc_base(void)
{
EPPC *retval;
asm volatile (
"mfspr %0,638 \n\t"
"andis. %0,%0,65535 \n\t"
: "=r" (retval)
: /* no inputs */ );
return retval;
}
// Function used to reset [only once!] the CPM
__externC void _mpc8xx_reset_cpm(void);
// Function used to allocate space in shared memory area
// typically used for buffer descriptors, etc.
__externC unsigned short _mpc8xx_allocBd(int len);
// Function used to manage the pool of baud rate generators
__externC unsigned long *_mpc8xx_allocate_brg(int port);
#define QUICC_BD_BASE 0x2000 // Start of shared memory
#define QUICC_BD_END 0x3000 // End of shared memory
#endif /* __ASSEMBLER__ */
/* Memory Periodic Timer Prescaler Register values */
#define PTP_DIV2 0x2000
#define PTP_DIV4 0x1000
#define PTP_DIV8 0x0800
#define PTP_DIV16 0x0400
#define PTP_DIV32 0x0200
#define PTP_DIV64 0x0100
// Command Processor Module (CPM)
// Buffer descriptor control bits
#define QUICC_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx)
#define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list
#define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx)
#define QUICC_BD_CTL_Last 0x0800 // Last buffer in a sequence
#define QUICC_BD_CTL_Frame 0x0010 // Framing Error
#define QUICC_BD_CTL_Parity 0x0008 // Parity Error
#define QUICC_BD_CTL_MASK 0xB000 // User settable bits
// Command register
#define QUICC_CPM_CR_INIT_TXRX 0x0000 // Initialize both Tx and Rx chains
#define QUICC_CPM_CR_INIT_RX 0x0100 // Initialize Rx chains
#define QUICC_CPM_CR_INIT_TX 0x0200 // Initialize Tx chains
#define QUICC_CPM_CR_HUNT_MODE 0x0300 // Start "hunt" mode
#define QUICC_CPM_CR_STOP_TX 0x0400 // Stop transmitter
#define QUICC_CPM_CR_RESTART_TX 0x0600 // Restart transmitter
#define QUICC_CPM_CR_RESET 0x8000 // Reset CPM
#define QUICC_CPM_CR_BUSY 0x0001 // Kick CPM - busy indicator
// CPM channels
#define QUICC_CPM_SCC1 0x0000
#define QUICC_CPM_I2C 0x0010
#define QUICC_CPM_SCC2 0x0040
#define QUICC_CPM_SCC3 0x0080
#define QUICC_CPM_SMC1 0x0090
#define QUICC_CPM_SCC4 0x00C0
#define QUICC_CPM_SMC2 0x00D0
// SMC Events (interrupts)
#define QUICC_SMCE_BRK 0x10 // Break received
#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
#define QUICC_SMCE_TX 0x02 // Tx interrupt
#define QUICC_SMCE_RX 0x01 // Rx interrupt
// SMC Mode Register
#define QUICC_SMCMR_CLEN(n) (n<<11) // Character length + parity + stop bits
#define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
#define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
#define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
#define QUICC_SMCMR_UART (2<<4) // UART mode
#define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
#define QUICC_SMCMR_REN (1<<0) // Enable receiver
// SMC Commands
#define QUICC_SMC_CMD_InitTxRx (0<<8)
#define QUICC_SMC_CMD_InitTx (1<<8)
#define QUICC_SMC_CMD_InitRx (2<<8)
#define QUICC_SMC_CMD_StopTx (4<<8)
#define QUICC_SMC_CMD_RestartTx (6<<8)
#define QUICC_SMC_CMD_Reset 0x8000
#define QUICC_SMC_CMD_Go 0x0001
// SCC PSMR masks ....
#define QUICC_SCC_PSMR_ASYNC 0x8000
#define QUICC_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb)
#define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8)
#define QUICC_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled)
#define QUICC_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high)
#define QUICC_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high)
// SCC DSR masks
#define QUICC_SCC_DSR_FULL 0x7e7e
#define QUICC_SCC_DSR_HALF 0x467e
// SCC GSMR masks ...
#define QUICC_SCC_GSMR_H_INIT 0x00000060
#define QUICC_SCC_GSMR_L_INIT 0x00028004
#define QUICC_SCC_GSMR_L_Tx 0x00000010
#define QUICC_SCC_GSMR_L_Rx 0x00000020
// SCC Events (interrupts)
#define QUICC_SCCE_BRK 0x0040
#define QUICC_SCCE_BSY 0x0004
#define QUICC_SCCE_TX 0x0002
#define QUICC_SCCE_RX 0x0001
#endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
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