📄 ppc8xx.h
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unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned long rcrc; /* temp receive CRC */
unsigned long tcrc; /* temp transmit CRC */
/*
* TRANSPARENT specific parameter RAM
*/
unsigned long crc_p; /* CRC Preset */
unsigned long crc_c; /* CRC constant */
};
struct timer_pram {
/*
* RISC timers parameter RAM
*/
unsigned short tm_base; /* RISC timer table base adr */
unsigned short tm_ptr; /* RISC timer table pointer */
unsigned short r_tmr; /* RISC timer mode register */
unsigned short r_tmv; /* RISC timer valid register */
unsigned long tm_cmd; /* RISC timer cmd register */
unsigned long tm_cnt; /* RISC timer internal cnt */
};
struct ucode_pram {
/*
* RISC ucode parameter RAM
*/
unsigned short rev_num; /* Ucode Revision Number */
unsigned short d_ptr; /* MISC Dump area pointer */
unsigned long temp1; /* MISC Temp1 */
unsigned long temp2; /* MISC Temp2 */
};
struct i2c_pram {
/*
* I2C parameter RAM
*/
unsigned short rbase; /* RX BD base address */
unsigned short tbase; /* TX BD base address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp[2]; /* Tx temp */
unsigned short rpbase; /* Relocated param block pointer */
unsigned short res; /* unused */
};
/*
* definitions of EPPC memory structures
*/
typedef struct eppc {
/* BASE + 0x0000: INTERNAL REGISTERS */
/* SIU */
volatile unsigned long siu_mcr; /* module configuration reg */
volatile unsigned long siu_sypcr; /* System protection cnt */
unsigned char RSRVD58[0x6];
volatile unsigned short siu_swsr; /* sw service */
volatile unsigned long siu_sipend; /* Interrupt pend reg */
volatile unsigned long siu_simask; /* Interrupt mask reg */
volatile unsigned long siu_siel; /* Interrupt edge level mask reg */
volatile unsigned long siu_sivec; /* Interrupt vector */
volatile unsigned long siu_tesr; /* Transfer error status */
volatile unsigned char RSRVD1[0xc];
volatile unsigned long dma_sdcr; /* SDMA configuration reg */
unsigned char RSRVD55[0x4c];
/* PCMCIA */
volatile unsigned long pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
volatile unsigned long pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
volatile unsigned long pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
volatile unsigned long pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
volatile unsigned long pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
volatile unsigned long pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
volatile unsigned long pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
volatile unsigned long pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
volatile unsigned long pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
volatile unsigned long pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
volatile unsigned long pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
volatile unsigned long pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
volatile unsigned long pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
volatile unsigned long pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
volatile unsigned long pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
volatile unsigned long pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
volatile unsigned char RSRVD2[0x20];
volatile unsigned long pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
volatile unsigned long pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
volatile unsigned long pcmcia_pscr; /* PCMCIA Status Reg */
volatile unsigned char RSRVD2a[0x4];
volatile unsigned long pcmcia_pipr; /* PCMCIA Pins Value Reg */
volatile unsigned char RSRVD2b[0x4];
volatile unsigned long pcmcia_per; /* PCMCIA Enable Reg */
volatile unsigned char RSRVD2c[0x4];
/* MEMC */
volatile unsigned long memc_br0; /* base register 0 */
volatile unsigned long memc_or0; /* option register 0 */
volatile unsigned long memc_br1; /* base register 1 */
volatile unsigned long memc_or1; /* option register 1 */
volatile unsigned long memc_br2; /* base register 2 */
volatile unsigned long memc_or2; /* option register 2 */
volatile unsigned long memc_br3; /* base register 3 */
volatile unsigned long memc_or3; /* option register 3 */
volatile unsigned long memc_br4; /* base register 3 */
volatile unsigned long memc_or4; /* option register 3 */
volatile unsigned long memc_br5; /* base register 3 */
volatile unsigned long memc_or5; /* option register 3 */
volatile unsigned long memc_br6; /* base register 3 */
volatile unsigned long memc_or6; /* option register 3 */
volatile unsigned long memc_br7; /* base register 3 */
volatile unsigned long memc_or7; /* option register 3 */
volatile unsigned char RSRVD3[0x24];
volatile unsigned long memc_mar; /* Memory address */
volatile unsigned long memc_mcr; /* Memory command */
volatile unsigned char RSRVD4[0x4];
volatile unsigned long memc_mamr; /* Machine A mode */
volatile unsigned long memc_mbmr; /* Machine B mode */
volatile unsigned short memc_mstat; /* Memory status */
volatile unsigned short memc_mptpr; /* Memory preidic timer prescalar */
volatile unsigned long memc_mdr; /* Memory data */
volatile unsigned char RSRVD5[0x80];
/* SYSTEM INTEGRATION TIMERS */
volatile unsigned short simt_tbscr; /* Time base stat&ctr */
volatile unsigned char RSRVD100[0x2];
volatile unsigned long simt_tbreff0; /* Time base reference 0 */
volatile unsigned long simt_tbreff1; /* Time base reference 1 */
volatile unsigned char RSRVD6[0x14];
volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */
volatile unsigned char RSRVD110[0x2];
volatile unsigned long simt_rtc; /* Realtime clock */
volatile unsigned long simt_rtsec; /* Realtime alarm seconds */
volatile unsigned long simt_rtcal; /* Realtime alarm */
volatile unsigned char RSRVD56[0x10];
volatile unsigned long simt_piscr; /* PIT stat&ctrl */
volatile unsigned long simt_pitc; /* PIT counter */
volatile unsigned long simt_pitr; /* PIT */
volatile unsigned char RSRVD7[0x34];
/* CLOCKS, RESET */
volatile unsigned long clkr_sccr; /* System clk cntrl */
volatile unsigned long clkr_plprcr; /* PLL reset&ctrl */
volatile unsigned long clkr_rsr; /* reset status */
volatile unsigned char RSRVD66a[0x74];
/* System Integration Timers Keys */
volatile unsigned long simt_tbscrk; /* Timebase Status&Ctrl Key */
volatile unsigned long simt_tbreff0k; /* Timebase Reference 0 Key */
volatile unsigned long simt_tbreff1k; /* Timebase Reference 1 Key */
volatile unsigned long simt_tbk; /* Timebase and Decrementer Key */
volatile unsigned char RSRVD66b[0x10];
volatile unsigned long simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
volatile unsigned long simt_rtck; /* Real-Time Clock Key */
volatile unsigned long simt_rtseck; /* Real-Time Alarm Seconds Key */
volatile unsigned long simt_rtcalk; /* Real-Time Alarm Key */
volatile unsigned char RSRVD66c[0x10];
volatile unsigned long simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
volatile unsigned long simt_pitck; /* Periodic Interrupt Count Key */
volatile unsigned char RSRVD66d[0x38];
/* Clock and Reset Keys */
volatile unsigned long clkr_sccrk; /* System Clock Control Key */
volatile unsigned long clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
volatile unsigned long clkr_rsrk; /* Reset Status Key */
volatile unsigned char RSRVD66e[0x4b4];
volatile unsigned long lcd_lccr; /* configuration Reg */
volatile unsigned long lcd_lchcr; /* Horizontal ctl Reg */
volatile unsigned long lcd_lcvcr; /* Vertical ctl Reg */
unsigned char RSRVD67[4];
volatile unsigned long lcd_lcfaa; /* Frame buffer A Address */
volatile unsigned long lcd_lcfba; /* Frame buffer B Address */
volatile unsigned char lcd_lcsr; /* Status Reg */
volatile unsigned char RSRVD9[0x7];
/* I2C */
volatile unsigned char i2c_i2mod; /* i2c mode */
unsigned char RSRVD59[3];
volatile unsigned char i2c_i2add; /* i2c address */
unsigned char RSRVD60[3];
volatile unsigned char i2c_i2brg; /* i2c brg */
unsigned char RSRVD61[3];
volatile unsigned char i2c_i2com; /* i2c command */
unsigned char RSRVD62[3];
volatile unsigned char i2c_i2cer; /* i2c event */
unsigned char RSRVD63[3];
volatile unsigned char i2c_i2cmr; /* i2c mask */
volatile unsigned char RSRVD10[0x0b];
volatile unsigned char i2c_spare_pram[0x80]; /* Used by patched ucode */
/* DMA */
volatile unsigned char RSRVD11[0x4];
volatile unsigned long dma_sdar; /* SDMA address reg */
volatile unsigned char dma_sdsr; /* SDMA status reg */
volatile unsigned char RSRVD12[0x3];
volatile unsigned char dma_sdmr; /* SDMA mask reg */
volatile unsigned char RSRVD13[0x3];
volatile unsigned char dma_idsr1; /* IDMA1 status reg */
volatile unsigned char RSRVD14[0x3];
volatile unsigned char dma_idmr1; /* IDMA1 mask reg */
volatile unsigned char RSRVD15[0x3];
volatile unsigned char dma_idsr2; /* IDMA2 status reg */
volatile unsigned char RSRVD16[0x3];
volatile unsigned char dma_idmr2; /* IDMA2 mask reg */
volatile unsigned char RSRVD17[0x13];
/* CPM Interrupt Controller */
volatile unsigned short cpmi_civr; /* CP interrupt vector reg */
volatile unsigned char RSRVD19[0xe];
volatile unsigned long cpmi_cicr; /* CP interrupt configuration reg */
volatile unsigned long cpmi_cipr; /* CP interrupt pending reg */
volatile unsigned long cpmi_cimr; /* CP interrupt mask reg */
volatile unsigned long cpmi_cisr; /* CP interrupt in-service reg */
/* I/O port */
volatile unsigned short pio_padir; /* port A data direction reg */
volatile unsigned short pio_papar; /* port A pin assignment reg */
volatile unsigned short pio_paodr; /* port A open drain reg */
volatile unsigned short pio_padat; /* port A data register */
volatile unsigned char RSRVD20[0x8];
volatile unsigned short pio_pcdir; /* port C data direction reg */
volatile unsigned short pio_pcpar; /* port C pin assignment reg */
volatile unsigned short pio_pcso; /* port C special options */
volatile unsigned short pio_pcdat; /* port C data register */
volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
unsigned char RSRVD64[6];
volatile unsigned short pio_pddir; /* port D Data Direction reg */
volatile unsigned short pio_pdpar; /* port D pin assignment reg */
unsigned char RSRVD65[2];
volatile unsigned short pio_pddat; /* port D data reg */
volatile unsigned char RSRVD21[0x8];
/* CPM Timer */
volatile unsigned short timer_tgcr; /* timer global configuration reg */
volatile unsigned char RSRVD22[0xe];
volatile unsigned short timer_tmr1; /* timer 1 mode reg */
volatile unsigned short timer_tmr2; /* timer 2 mode reg */
volatile unsigned short timer_trr1; /* timer 1 referance reg */
volatile unsigned short timer_trr2; /* timer 2 referance reg */
volatile unsigned short timer_tcr1; /* timer 1 capture reg */
volatile unsigned short timer_tcr2; /* timer 2 capture reg */
volatile unsigned short timer_tcn1; /* timer 1 counter reg */
volatile unsigned short timer_tcn2; /* timer 2 counter reg */
volatile unsigned short timer_tmr3; /* timer 3 mode reg */
volatile unsigned short timer_tmr4; /* timer 4 mode reg */
volatile unsigned short timer_trr3; /* timer 3 referance reg */
volatile unsigned short timer_trr4; /* timer 4 referance reg */
volatile unsigned short timer_tcr3; /* timer 3 capture reg */
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