ppc8xx.h

开放源码实时操作系统源码.

#ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
#define CYGONCE_HAL_PPC_QUICC_PPC8XX_H

//==========================================================================
//
//      ppc8xx.h
//
//      PowerPC QUICC register definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Red Hat
// Contributors: hmt
// Date:         1999-06-08
// Purpose:      Provide PPC QUICC definitions
// Description:  Provide PPC QUICC definitions
// Usage:        THIS IS NOT AN EXTERNAL API
//               This file is in the include dir to share it between
//               QUICC serial code and MBX initialization code.
//               #include <cyg/hal/quicc/ppc8xx.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#ifdef __ASSEMBLER__

#define SIUMCR     0x000        /* SIU Module configuration */
#define SYPCR      0x004        /* SIU System Protection Control */
#define SIPEND     0x010        /* SIU Interrupt Pending Register */
#define SIMASK     0x014        /* SIU Interrupt MASK Register */
#define SIEL       0x018        /* SIU Interrupt Edge/Level Register */
#define SIVEC      0x01C        /* SIU Interrupt Vector Register */
#define SDCR       0x030        /* SDMA Config Register */
#define BR0        0x100        /* Base Register 0 */
#define OR0        0x104        /* Option Register 0 */
#define BR1        0x108        /* Base Register 1 */
#define OR1        0x10C        /* Option Register 1 */
#define BR2        0x110        /* Base Register 2 */
#define OR2        0x114        /* Option Register 2 */
#define BR3        0x118        /* Base Register 2 */
#define OR3        0x11C        /* Option Register 2 */
#define BR4        0x120        /* Base Register 2 */
#define OR4        0x124        /* Option Register 2 */
#define BR5        0x128        /* Base Register 2 */
#define OR5        0x12C        /* Option Register 2 */
#define BR6        0x130        /* Base Register 2 */
#define OR6        0x134        /* Option Register 2 */
#define BR7        0x138        /* Base Register 2 */
#define OR7        0x13C        /* Option Register 2 */
#define MAR        0x164        /* Memory Address */
#define MCR        0x168        /* Memory Command */
#define MAMR       0x170        /* Machine A Mode Register */
#define MBMR       0x174        /* Machine B Mode Register */
#define MPTPR      0x17A        /* Memory Periodic Timer Prescaler */
#define MDR        0x17C        /* Memory Data */
#define TBSCR      0x200        /* Time Base Status and Control Register */
#define RTCSC      0x220        /* Real Timer Clock Status and Control */
#define PISCR      0x240        /* PIT Status and Control */
#define SCCR       0x280        /* System Clock Control Register */
#define PLPRCR     0x284        /* PLL, Low power & Reset Control Register */
#define RTCSCK     0x320
#define RTCK       0x324
#define RTSECK     0x328
#define RTCALK     0x32C
#define PADIR      0x950        /* Port A - Pin direction */
#define PAPAR      0x952        /* Port A - Pin assignment */
#define PAODR      0x954        /* Port A - Open Drain Control */
#define PADAT      0x956        /* Port A - Data */

#else

#include <cyg/infra/cyg_type.h>

/*****************************************************************
	Communications Processor Buffer Descriptor
*****************************************************************/
struct cp_bufdesc {
    volatile unsigned short ctrl;	/* status/control register */
    volatile unsigned short length;	/* buffer length */
    volatile char  	    *buffer;	/* buffer pointer */
};

/*****************************************************************
	HDLC parameter RAM
*****************************************************************/

struct hdlc_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short	rbase;		/* RX BD base address */
    unsigned short	tbase;		/* TX BD base address */
    unsigned char	rfcr;		/* Rx function code */
    unsigned char	tfcr;		/* Tx function code */
    unsigned short	mrblr;		/* Rx buffer length */
    unsigned long	rstate;		/* Rx internal state */
    unsigned long	rptr;		/* Rx internal data pointer */
    unsigned short	rbptr;		/* rb BD Pointer */
    unsigned short	rcount;		/* Rx internal byte count */
    unsigned long	rtemp;		/* Rx temp */
    unsigned long	tstate;		/* Tx internal state */
    unsigned long	tptr;		/* Tx internal data pointer */
    unsigned short	tbptr;		/* Tx BD pointer */
    unsigned short	tcount;		/* Tx byte count */
    unsigned long	ttemp;		/* Tx temp */
    unsigned long	rcrc;		/* temp receive CRC */
    unsigned long	tcrc;		/* temp transmit CRC */

    /*
     * HDLC specific parameter RAM
     */
    unsigned char	RSRVD1[4];	
    unsigned long	c_mask;		/* CRC constant */
    unsigned long	c_pres;		/* CRC preset */
    unsigned short	disfc;		/* discarded frame counter */
    unsigned short	crcec;		/* CRC error counter */
    unsigned short	abtsc;		/* abort sequence counter */
    unsigned short	nmarc;		/* nonmatching address rx cnt */
    unsigned short	retrc;		/* frame retransmission cnt */
    unsigned short	mflr;		/* maximum frame length reg */
    unsigned short	max_cnt;	/* maximum length counter */
    unsigned short	rfthr;		/* received frames threshold */
    unsigned short	rfcnt;		/* received frames count */
    unsigned short	hmask;		/* user defined frm addr mask */
    unsigned short	haddr1;		/* user defined frm address 1 */
    unsigned short	haddr2;		/* user defined frm address 2 */
    unsigned short	haddr3;		/* user defined frm address 3 */
    unsigned short	haddr4;		/* user defined frm address 4 */
    unsigned short	tmp;		/* temp */
    unsigned short	tmp_mb;		/* temp */
};


/*****************************************************************
	ASYNC HDLC parameter RAM
*****************************************************************/

struct async_hdlc_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short	rbase;		/* RX BD base address */
    unsigned short	tbase;		/* TX BD base address */
    unsigned char	rfcr;		/* Rx function code */
    unsigned char	tfcr;		/* Tx function code */
    unsigned short	mrblr;		/* Rx buffer length */
    unsigned long	rstate;		/* Rx internal state */
    unsigned long	rptr;		/* Rx internal data pointer */
    unsigned short	rbptr;		/* rb BD Pointer */
    unsigned short	rcount;		/* Rx internal byte count */
    unsigned long	rtemp;		/* Rx temp */
    unsigned long	tstate;		/* Tx internal state */
    unsigned long	tptr;		/* Tx internal data pointer */
    unsigned short	tbptr;		/* Tx BD pointer */
    unsigned short	tcount;		/* Tx byte count */
    unsigned long	ttemp;		/* Tx temp */
    unsigned long	rcrc;		/* temp receive CRC */
    unsigned long	tcrc;		/* temp transmit CRC */

    /*
     * ASYNC HDLC specific parameter RAM
     */
    unsigned char	RSRVD1[4];	
    unsigned long	c_mask;		/* CRC constant */
    unsigned long	c_pres;		/* CRC preset */
    unsigned short	bof;		/* begining of flag character */
    unsigned short	eof;		/* end of flag character */
    unsigned short	esc;		/* control escape character */
    unsigned char	RSRVD2[4];	
    unsigned short	zero;		/* zero */
    unsigned char	RSRVD3[2];	
    unsigned short	rfthr;		/* received frames threshold */
    unsigned char	RSRVD4[4];	
    unsigned long	txctl_tbl;	/* Tx ctl char mapping table */
    unsigned long	rxctl_tbl;	/* Rx ctl char mapping table */
    unsigned short	nof;		/* Number of opening flags */
};


/*****************************************************************
	UART parameter RAM
*****************************************************************/

/*
 * bits in uart control characters table
 */
#define	CC_INVALID	0x8000		/* control character is valid */
#define	CC_REJ		0x4000		/* don't store char in buffer */
#define	CC_CHAR		0x00ff		/* control character */

/* UART */
struct uart_pram {
    /*
     * SCC parameter RAM
     */
    unsigned short	rbase;		/* RX BD base address */
    unsigned short	tbase;		/* TX BD base address */
    unsigned char	rfcr;		/* Rx function code */
    unsigned char	tfcr;		/* Tx function code */
    unsigned short	mrblr;		/* Rx buffer length */
    unsigned long	rstate;		/* Rx internal state */
    unsigned long	rptr;		/* Rx internal data pointer */
    unsigned short	rbptr;		/* rb BD Pointer */
    unsigned short	rcount;		/* Rx internal byte count */
    unsigned long	rx_temp;	/* Rx temp */
    unsigned long	tstate;		/* Tx internal state */
    unsigned long	tptr;		/* Tx internal data pointer */
    unsigned short	tbptr;		/* Tx BD pointer */
    unsigned short	tcount;		/* Tx byte count */
    unsigned long	ttemp;		/* Tx temp */
    unsigned long	rcrc;		/* temp receive CRC */
    unsigned long	tcrc;		/* temp transmit CRC */

    /*
     * UART specific parameter RAM
     */
    unsigned char	RSRVD1[8];	
    unsigned short	max_idl;	/* maximum idle characters */
    unsigned short	idlc;		/* rx idle counter (internal) */
    unsigned short	brkcr;		/* break count register */

    unsigned short	parec;		/* Rx parity error counter */
    unsigned short	frmer;		/* Rx framing error counter */