📄 ppc_860.h
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/*-----*/
/* SPI */
/*-----*/
volatile cyg_uint16 spi_spmode; /* SPI mode reg */
volatile cyg_uint8 RESERVED67[0x4]; /* Reserved area */
volatile cyg_uint8 spi_spie; /* SPI event reg */
volatile cyg_uint8 RESERVED68[0x3]; /* Reserved area */
volatile cyg_uint8 spi_spim; /* SPI mask reg */
volatile cyg_uint8 RESERVED69[0x2]; /* Reserved area */
volatile cyg_uint8 spi_spcom; /* SPI command reg */
volatile cyg_uint8 RESERVED70[0x4]; /* Reserved area */
/*-----*/
/* PIP */
/*-----*/
volatile cyg_uint16 pip_pipc; /* pip configuration reg */
volatile cyg_uint8 RESERVED71[0x2]; /* Reserved area */
volatile cyg_uint16 pip_ptpr; /* pip timing parameters reg */
volatile cyg_uint32 pip_pbdir; /* port b data direction reg */
volatile cyg_uint32 pip_pbpar; /* port b pin assignment reg */
volatile cyg_uint8 RESERVED72[0x2]; /* Reserved area */
volatile cyg_uint16 pip_pbodr; /* port b open drain reg */
volatile cyg_uint32 pip_pbdat; /* port b data reg */
volatile cyg_uint8 RESERVED73[0x18]; /* Reserved area */
/*------------------*/
/* Serial Interface */
/*------------------*/
volatile cyg_uint32 si_simode; /* SI mode register */
volatile cyg_uint8 si_sigmr; /* SI global mode register */
volatile cyg_uint8 RESERVED74; /* Reserved area */
volatile cyg_uint8 si_sistr; /* SI status register */
volatile cyg_uint8 si_sicmr; /* SI command register */
volatile cyg_uint8 RESERVED75[0x4]; /* Reserved area */
volatile cyg_uint32 si_sicr; /* SI clock routing */
volatile cyg_uint32 si_sirp; /* SI ram pointers */
volatile cyg_uint8 RESERVED76[0x10c]; /* Reserved area */
volatile cyg_uint8 si_siram[0x200]; /* SI routing ram */
volatile cyg_uint8 RESERVED77[0x1200]; /* Reserved area */
/*-----------------------------------------------------------------*/
/* BASE + 0x2000: user data memory, microcode, or QMC channel PRAM */
/*-----------------------------------------------------------------*/
union
{
struct qmc_chan_pram qcp[64];
struct user_data ud;
cyg_uint8 RESERVED[0x1c00];
} qcp_or_ud;
/*-----------------------------------------------------------------------*/
/* BASE + 0x3c00: PARAMETER RAM. This main union defines 4 memory blocks */
/* of an identical size. See the Parameter RAM definition in the MPC860 */
/* user's manual. */
/*-----------------------------------------------------------------------*/
/*------------------------*/
/* Base + 0x3C00 (page 1) */
/* + 0x3D00 (page 2) */
/* + 0x3E00 (page 3) */
/* + 0x3F00 (page 4) */
/*------------------------*/
union
{
struct page_of_pram
{
/*------------------------------------------------------------*/
/* scc parameter area - 1st memory block (protocol dependent) */
/*------------------------------------------------------------*/
union
{
struct hdlc_pram h;
struct uart_pram u;
struct bisync_pram b;
struct transparent_pram t;
struct async_hdlc_pram a;
cyg_uint8 RESERVED78[0x80];
} scc;
/*----------------------------------------------------------------*/
/* Other protocol areas for the rest of the memory blocks in each */
/* page. */
/*----------------------------------------------------------------*/
union
{
/*---------------------------------------------------------------*/
/* This structure defines the rest of the blocks on the 1st page */
/*---------------------------------------------------------------*/
struct
{
struct i2c_pram i2c; /* I2C */
struct misc_pram misc; /* MISC */
struct idma_pram idma1; /* IDMA1 */
} i2c_idma;
/*---------------------------------------------------------------*/
/* This structure defines the rest of the blocks on the 2nd page */
/*---------------------------------------------------------------*/
struct
{
struct spi_pram spi; /* SPI */
struct timer_pram timer; /* Timers */
struct idma_pram idma2; /* IDMA2 */
} spi_timer_idma;
/*---------------------------------------------------------------*/
/* This structure defines the rest of the blocks on the 3rd page */
/*---------------------------------------------------------------*/
struct
{
union
{
struct smc_uart_pram u1; /* SMC1 */
struct smc_trnsp_pram t1; /* SMC1 */
cyg_uint8 RESERVED78[0x80]; /* declare full block */
} psmc1;
} smc_dsp1;
/*---------------------------------------------------------------*/
/* This structure defines the rest of the blocks on the 4th page */
/*---------------------------------------------------------------*/
struct
{
union
{
struct smc_uart_pram u2; /* SMC2 */
struct smc_trnsp_pram t2; /* SMC2 */
struct centronics_pram c; /* Uses SM2's space */
cyg_uint8 RESERVED79[0x80]; /* declare full block */
} psmc2;
} smc_dsp2;
cyg_uint8 RESERVED80[0x80]; /* declare full block */
} other;
} pg;
/*---------------------------------------------------------------*/
/* When selecting Ethernet as protocol for an SCC, this protocol */
/* uses a complete page of Parameter RAM memory. */
/*---------------------------------------------------------------*/
struct ethernet_pram enet_scc;
/*---------------------------------------------------------------*/
/* When using QMC as a mode for an SCC, the QMC global parameter */
/* ram uses from SCC BASE to BASE+AC. */
/*---------------------------------------------------------------*/
struct global_qmc_pram gqp;
/*--------------------------------------------------------*/
/* declaration to guarantee a page of memory is allocated */
/*--------------------------------------------------------*/
cyg_uint8 RESERVED83[0x100];
} PRAM[4]; /* end of union */
} EPPC;
/***************************************************************************/
/* General Global Definitions */
/***************************************************************************/
#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */
#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */
#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */
#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */
#define SCC1_REG 0 /* SCC1 Index into SCC Regs Array */
#define SCC2_REG 1 /* SCC2 Index into SCC Regs Array */
#define SCC3_REG 2 /* SCC3 Index into SCC Regs Array */
#define SCC4_REG 3 /* SCC4 Index into SCC Regs Array */
/*--------------------------------*/
/* KEEP ALIVE POWER REGISTERS KEY */
/*--------------------------------*/
#define KEEP_ALIVE_KEY 0x55ccaa33
#define SMC2_REG 1 /* SMC Regs Array Index for SMC2 */
/*-------------------------*/
/* Single buffer component */
/*-------------------------*/
typedef struct BufferPool
{
cyg_uint8 RxBuffer;
cyg_uint8 TxBuffer;
} LB;
/*--------------------------*/
/* Buffer Descriptor Format */
/*--------------------------*/
typedef struct BufferDescriptor
{
cyg_uint16 bd_cstatus; /* control and status */
cyg_uint16 bd_length; /* transfer length */
cyg_uint8 *bd_addr; /* buffer address */
} BD;
/*-------------------------------*/
/* Buffer Descriptor Ring format */
/*-------------------------------*/
typedef struct BufferDescRings
{
volatile BD RxBD; /* Rx BD ring */
volatile BD TxBD; /* Tx BD ring */
} BDRINGS;
#endif /* CYGONCE_HAL_PPC_FADS_PPC_860_H */
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