📄 ppc_860.h
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volatile cyg_uint32 pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
volatile cyg_uint32 pcmcia_pscr; /* PCMCIA Status Reg */
volatile cyg_uint8 RESERVED17[0x4]; /* Reserved area */
volatile cyg_uint32 pcmcia_pipr; /* PCMCIA Pins Value Reg */
volatile cyg_uint8 RESERVED18[0x4]; /* Reserved area */
volatile cyg_uint32 pcmcia_per; /* PCMCIA Enable Reg */
volatile cyg_uint8 RESERVED19[0x4]; /* Reserved area */
/*------*/
/* MEMC */
/*------*/
volatile cyg_uint32 memc_br0; /* base register 0 */
volatile cyg_uint32 memc_or0; /* option register 0 */
volatile cyg_uint32 memc_br1; /* base register 1 */
volatile cyg_uint32 memc_or1; /* option register 1 */
volatile cyg_uint32 memc_br2; /* base register 2 */
volatile cyg_uint32 memc_or2; /* option register 2 */
volatile cyg_uint32 memc_br3; /* base register 3 */
volatile cyg_uint32 memc_or3; /* option register 3 */
volatile cyg_uint32 memc_br4; /* base register 3 */
volatile cyg_uint32 memc_or4; /* option register 3 */
volatile cyg_uint32 memc_br5; /* base register 3 */
volatile cyg_uint32 memc_or5; /* option register 3 */
volatile cyg_uint32 memc_br6; /* base register 3 */
volatile cyg_uint32 memc_or6; /* option register 3 */
volatile cyg_uint32 memc_br7; /* base register 3 */
volatile cyg_uint32 memc_or7; /* option register 3 */
volatile cyg_uint8 RESERVED20[0x24]; /* Reserved area */
volatile cyg_uint32 memc_mar; /* Memory address */
volatile cyg_uint32 memc_mcr; /* Memory command */
volatile cyg_uint8 RESERVED21[0x4]; /* Reserved area */
volatile cyg_uint32 memc_mamr; /* Machine A mode */
volatile cyg_uint32 memc_mbmr; /* Machine B mode */
volatile cyg_uint16 memc_mstat; /* Memory status */
volatile cyg_uint16 memc_mptpr; /* Memory preidic timer prescalar */
volatile cyg_uint32 memc_mdr; /* Memory data */
volatile cyg_uint8 RESERVED22[0x80]; /* Reserved area */
/*---------------------------*/
/* SYSTEM INTEGRATION TIMERS */
/*---------------------------*/
volatile cyg_uint16 simt_tbscr; /* Time base stat&ctr */
volatile cyg_uint8 RESERVED23[0x2]; /* Reserved area */
volatile cyg_uint32 simt_tbreff0; /* Time base reference 0 */
volatile cyg_uint32 simt_tbreff1; /* Time base reference 1 */
volatile cyg_uint8 RESERVED24[0x14]; /* Reserved area */
volatile cyg_uint16 simt_rtcsc; /* Realtime clk stat&cntr 1 */
volatile cyg_uint8 RESERVED25[0x2]; /* Reserved area */
volatile cyg_uint32 simt_rtc; /* Realtime clock */
volatile cyg_uint32 simt_rtsec; /* Realtime alarm seconds */
volatile cyg_uint32 simt_rtcal; /* Realtime alarm */
volatile cyg_uint8 RESERVED26[0x10]; /* Reserved area */
volatile cyg_uint32 simt_piscr; /* PIT stat&ctrl */
volatile cyg_uint32 simt_pitc; /* PIT counter */
volatile cyg_uint32 simt_pitr; /* PIT */
volatile cyg_uint8 RESERVED27[0x34]; /* Reserved area */
/*---------------*/
/* CLOCKS, RESET */
/*---------------*/
volatile cyg_uint32 clkr_sccr; /* System clk cntrl */
volatile cyg_uint32 clkr_plprcr; /* PLL reset&ctrl */
volatile cyg_uint32 clkr_rsr; /* reset status */
cyg_uint8 RESERVED28[0x74]; /* Reserved area */
/*--------------------------------*/
/* System Integration Timers Keys */
/*--------------------------------*/
volatile cyg_uint32 simt_tbscrk; /* Timebase Status&Ctrl Key */
volatile cyg_uint32 simt_tbreff0k; /* Timebase Reference 0 Key */
volatile cyg_uint32 simt_tbreff1k; /* Timebase Reference 1 Key */
volatile cyg_uint32 simt_tbk; /* Timebase and Decrementer Key */
cyg_uint8 RESERVED29[0x10]; /* Reserved area */
volatile cyg_uint32 simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
volatile cyg_uint32 simt_rtck; /* Real-Time Clock Key */
volatile cyg_uint32 simt_rtseck; /* Real-Time Alarm Seconds Key */
volatile cyg_uint32 simt_rtcalk; /* Real-Time Alarm Key */
cyg_uint8 RESERVED30[0x10]; /* Reserved area */
volatile cyg_uint32 simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
volatile cyg_uint32 simt_pitck; /* Periodic Interrupt Count Key */
cyg_uint8 RESERVED31[0x38]; /* Reserved area */
/*----------------------*/
/* Clock and Reset Keys */
/*----------------------*/
volatile cyg_uint32 clkr_sccrk; /* System Clock Control Key */
volatile cyg_uint32 clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
volatile cyg_uint32 clkr_rsrk; /* Reset Status Key */
cyg_uint8 RESERVED32[0x4d4]; /* Reserved area */
/*-----*/
/* I2C */
/*-----*/
volatile cyg_uint8 i2c_i2mod; /* i2c mode */
cyg_uint8 RESERVED33[3];
volatile cyg_uint8 i2c_i2add; /* i2c address */
cyg_uint8 RESERVED34[3];
volatile cyg_uint8 i2c_i2brg; /* i2c brg */
cyg_uint8 RESERVED35[3];
volatile cyg_uint8 i2c_i2com; /* i2c command */
cyg_uint8 RESERVED36[3];
volatile cyg_uint8 i2c_i2cer; /* i2c event */
cyg_uint8 RESERVED37[3];
volatile cyg_uint8 i2c_i2cmr; /* i2c mask */
volatile cyg_uint8 RESERVED38[0x8b]; /* Reserved area */
/*-----*/
/* DMA */
/*-----*/
volatile cyg_uint8 RESERVED39[0x4]; /* Reserved area */
volatile cyg_uint32 dma_sdar; /* SDMA address reg */
volatile cyg_uint8 RESERVED40[0x2]; /* Reserved area */
volatile cyg_uint8 dma_sdsr; /* SDMA status reg */
volatile cyg_uint8 RESERVED41[0x3]; /* Reserved area */
volatile cyg_uint8 dma_sdmr; /* SDMA mask reg */
volatile cyg_uint8 RESERVED42[0x1]; /* Reserved area */
volatile cyg_uint8 dma_idsr1; /* IDMA1 status reg */
volatile cyg_uint8 RESERVED43[0x3]; /* Reserved area */
volatile cyg_uint8 dma_idmr1; /* IDMA1 mask reg */
volatile cyg_uint8 RESERVED44[0x3]; /* Reserved area */
volatile cyg_uint8 dma_idsr2; /* IDMA2 status reg */
volatile cyg_uint8 RESERVED45[0x3]; /* Reserved area */
volatile cyg_uint8 dma_idmr2; /* IDMA2 mask reg */
volatile cyg_uint8 RESERVED46[0x13]; /* Reserved area */
/*--------------------------*/
/* CPM Interrupt Controller */
/*--------------------------*/
volatile cyg_uint16 cpmi_civr; /* CP interrupt vector reg */
volatile cyg_uint8 RESERVED47[0xe]; /* Reserved area */
volatile cyg_uint32 cpmi_cicr; /* CP interrupt configuration reg */
volatile cyg_uint32 cpmi_cipr; /* CP interrupt pending reg */
volatile cyg_uint32 cpmi_cimr; /* CP interrupt mask reg */
volatile cyg_uint32 cpmi_cisr; /* CP interrupt in-service reg */
/*----------*/
/* I/O port */
/*----------*/
volatile cyg_uint16 pio_padir; /* port A data direction reg */
volatile cyg_uint16 pio_papar; /* port A pin assignment reg */
volatile cyg_uint16 pio_paodr; /* port A open drain reg */
volatile cyg_uint16 pio_padat; /* port A data register */
volatile cyg_uint8 RESERVED48[0x8]; /* Reserved area */
volatile cyg_uint16 pio_pcdir; /* port C data direction reg */
volatile cyg_uint16 pio_pcpar; /* port C pin assignment reg */
volatile cyg_uint16 pio_pcso; /* port C special options */
volatile cyg_uint16 pio_pcdat; /* port C data register */
volatile cyg_uint16 pio_pcint; /* port C interrupt cntrl reg */
cyg_uint8 RESERVED49[6];
volatile cyg_uint16 pio_pddir; /* port D Data Direction reg */
volatile cyg_uint16 pio_pdpar; /* port D pin assignment reg */
cyg_uint8 RESERVED50[2];
volatile cyg_uint16 pio_pddat; /* port D data reg */
volatile cyg_uint8 RESERVED51[0x8]; /* Reserved area */
/*-----------*/
/* CPM Timer */
/*-----------*/
volatile cyg_uint16 timer_tgcr; /* timer global configuration reg */
volatile cyg_uint8 RESERVED52[0xe]; /* Reserved area */
volatile cyg_uint16 timer_tmr1; /* timer 1 mode reg */
volatile cyg_uint16 timer_tmr2; /* timer 2 mode reg */
volatile cyg_uint16 timer_trr1; /* timer 1 referance reg */
volatile cyg_uint16 timer_trr2; /* timer 2 referance reg */
volatile cyg_uint16 timer_tcr1; /* timer 1 capture reg */
volatile cyg_uint16 timer_tcr2; /* timer 2 capture reg */
volatile cyg_uint16 timer_tcn1; /* timer 1 counter reg */
volatile cyg_uint16 timer_tcn2; /* timer 2 counter reg */
volatile cyg_uint16 timer_tmr3; /* timer 3 mode reg */
volatile cyg_uint16 timer_tmr4; /* timer 4 mode reg */
volatile cyg_uint16 timer_trr3; /* timer 3 referance reg */
volatile cyg_uint16 timer_trr4; /* timer 4 referance reg */
volatile cyg_uint16 timer_tcr3; /* timer 3 capture reg */
volatile cyg_uint16 timer_tcr4; /* timer 4 capture reg */
volatile cyg_uint16 timer_tcn3; /* timer 3 counter reg */
volatile cyg_uint16 timer_tcn4; /* timer 4 counter reg */
volatile cyg_uint16 timer_ter1; /* timer 1 event reg */
volatile cyg_uint16 timer_ter2; /* timer 2 event reg */
volatile cyg_uint16 timer_ter3; /* timer 3 event reg */
volatile cyg_uint16 timer_ter4; /* timer 4 event reg */
volatile cyg_uint8 RESERVED53[0x8]; /* Reserved area */
/*----*/
/* CP */
/*----*/
volatile cyg_uint16 cp_cr; /* command register */
volatile cyg_uint8 RESERVED54[0x2]; /* Reserved area */
volatile cyg_uint16 cp_rccr; /* main configuration reg */
volatile cyg_uint8 RESERVED55; /* Reserved area */
volatile cyg_uint8 cp_resv1; /* Reserved reg */
volatile cyg_uint32 cp_resv2; /* Reserved reg */
volatile cyg_uint16 cp_rctr1; /* ram break register 1 */
volatile cyg_uint16 cp_rctr2; /* ram break register 2 */
volatile cyg_uint16 cp_rctr3; /* ram break register 3 */
volatile cyg_uint16 cp_rctr4; /* ram break register 4 */
volatile cyg_uint8 RESERVED56[0x2]; /* Reserved area */
volatile cyg_uint16 cp_rter; /* RISC timers event reg */
volatile cyg_uint8 RESERVED57[0x2]; /* Reserved area */
volatile cyg_uint16 cp_rtmr; /* RISC timers mask reg */
volatile cyg_uint8 RESERVED58[0x14]; /* Reserved area */
/*-----*/
/* BRG */
/*-----*/
volatile cyg_uint32 brgc1; /* BRG1 configuration reg */
volatile cyg_uint32 brgc2; /* BRG2 configuration reg */
volatile cyg_uint32 brgc3; /* BRG3 configuration reg */
volatile cyg_uint32 brgc4; /* BRG4 configuration reg */
/*---------------*/
/* SCC registers */
/*---------------*/
struct scc_regs
{
volatile cyg_uint32 scc_gsmr_l; /* SCC Gen mode (LOW) */
volatile cyg_uint32 scc_gsmr_h; /* SCC Gen mode (HIGH) */
volatile cyg_uint16 scc_psmr; /* protocol specific mode register */
volatile cyg_uint8 RESERVED59[0x2]; /* Reserved area */
volatile cyg_uint16 scc_todr; /* SCC transmit on demand */
volatile cyg_uint16 scc_dsr; /* SCC data sync reg */
volatile cyg_uint16 scc_scce; /* SCC event reg */
volatile cyg_uint8 RESERVED60[0x2]; /* Reserved area */
volatile cyg_uint16 scc_sccm; /* SCC mask reg */
volatile cyg_uint8 RESERVED61[0x1]; /* Reserved area */
volatile cyg_uint8 scc_sccs; /* SCC status reg */
volatile cyg_uint8 RESERVED62[0x8]; /* Reserved area */
} scc_regs[4];
/*-----*/
/* SMC */
/*-----*/
struct smc_regs
{
volatile cyg_uint8 RESERVED63[0x2]; /* Reserved area */
volatile cyg_uint16 smc_smcmr; /* SMC mode reg */
volatile cyg_uint8 RESERVED64[0x2]; /* Reserved area */
volatile cyg_uint8 smc_smce; /* SMC event reg */
volatile cyg_uint8 RESERVED65[0x3]; /* Reserved area */
volatile cyg_uint8 smc_smcm; /* SMC mask reg */
volatile cyg_uint8 RESERVED66[0x5]; /* Reserved area */
} smc_regs[2];
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