📄 ppc_860.h
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cyg_uint32 rstate; /* Rx internal state */
cyg_uint32 rptr; /* Rx internal data pointer */
cyg_uint16 rbptr; /* rb BD Pointer */
cyg_uint16 rcount; /* Rx internal byte count */
cyg_uint32 rtemp; /* Rx temp */
cyg_uint32 tstate; /* Tx internal state */
cyg_uint32 tptr; /* Tx internal data pointer */
cyg_uint16 tbptr; /* Tx BD pointer */
cyg_uint16 tcount; /* Tx byte count */
cyg_uint32 ttemp; /* Tx temp */
cyg_uint16 RESERVED11[5]; /* Reserved */
};
/*--------------------------------------------------------------------------*/
/* SPI parameter RAM */
/*--------------------------------------------------------------------------*/
#define SPI_R 0x8000 /* Ready bit in BD */
struct spi_pram
{
cyg_uint16 rbase; /* Rx BD Base Address */
cyg_uint16 tbase; /* Tx BD Base Address */
cyg_uint8 rfcr; /* Rx function code */
cyg_uint8 tfcr; /* Tx function code */
cyg_uint16 mrblr; /* Rx buffer length */
cyg_uint32 rstate; /* Rx internal state */
cyg_uint32 rptr; /* Rx internal data pointer */
cyg_uint16 rbptr; /* rb BD Pointer */
cyg_uint16 rcount; /* Rx internal byte count */
cyg_uint32 rtemp; /* Rx temp */
cyg_uint32 tstate; /* Tx internal state */
cyg_uint32 tptr; /* Tx internal data pointer */
cyg_uint16 tbptr; /* Tx BD pointer */
cyg_uint16 tcount; /* Tx byte count */
cyg_uint32 ttemp; /* Tx temp */
cyg_uint8 RESERVED12[8]; /* Reserved */
};
/*--------------------------------------------------------------------------*/
/* I2C parameter RAM */
/*--------------------------------------------------------------------------*/
struct i2c_pram
{
/*--------------------*/
/* I2C parameter RAM */
/*--------------------*/
cyg_uint16 rbase; /* RX BD base address */
cyg_uint16 tbase; /* TX BD base address */
cyg_uint8 rfcr; /* Rx function code */
cyg_uint8 tfcr; /* Tx function code */
cyg_uint16 mrblr; /* Rx buffer length */
cyg_uint32 rstate; /* Rx internal state */
cyg_uint32 rptr; /* Rx internal data pointer */
cyg_uint16 rbptr; /* rb BD Pointer */
cyg_uint16 rcount; /* Rx internal byte count */
cyg_uint32 rtemp; /* Rx temp */
cyg_uint32 tstate; /* Tx internal state */
cyg_uint32 tptr; /* Tx internal data pointer */
cyg_uint16 tbptr; /* Tx BD pointer */
cyg_uint16 tcount; /* Tx byte count */
cyg_uint32 ttemp; /* Tx temp */
cyg_uint8 RESERVED13[8];
};
/*--------------------------------------------------------------------------*/
/* MISC parameter RAM */
/*--------------------------------------------------------------------------*/
struct misc_pram
{
cyg_uint8 RESERVED14[16];
};
/*--------------------------------------------------------------------------*/
/* PIP Centronics parameter RAM */
/*--------------------------------------------------------------------------*/
struct centronics_pram
{
cyg_uint16 rbase; /* Rx BD Base Address */
cyg_uint16 tbase; /* Tx BD Base Address */
cyg_uint8 fcr; /* function code */
cyg_uint8 smask; /* Status Mask */
cyg_uint16 mrblr; /* Rx buffer length */
cyg_uint32 rstate; /* Rx internal state */
cyg_uint32 rptr; /* Rx internal data pointer */
cyg_uint16 rbptr; /* rb BD Pointer */
cyg_uint16 rcount; /* Rx internal byte count */
cyg_uint32 rtemp; /* Rx temp */
cyg_uint32 tstate; /* Tx internal state */
cyg_uint32 tptr; /* Tx internal data pointer */
cyg_uint16 tbptr; /* Tx BD pointer */
cyg_uint16 tcount; /* Tx byte count */
cyg_uint32 ttemp; /* Tx temp */
cyg_uint16 max_sl; /* Maximum Silence period */
cyg_uint16 sl_cnt; /* Silence Counter */
cyg_uint16 char1; /* CONTROL char 1 */
cyg_uint16 char2; /* CONTROL char 2 */
cyg_uint16 char3; /* CONTROL char 3 */
cyg_uint16 char4; /* CONTROL char 4 */
cyg_uint16 char5; /* CONTROL char 5 */
cyg_uint16 char6; /* CONTROL char 6 */
cyg_uint16 char7; /* CONTROL char 7 */
cyg_uint16 char8; /* CONTROL char 8 */
cyg_uint16 rccm; /* Rx Control Char Mask */
cyg_uint16 rccr; /* Rx Char Control Register */
};
/*--------------------------------------------------------------------------*/
/* IDMA parameter RAM */
/*--------------------------------------------------------------------------*/
struct idma_pram
{
cyg_uint16 ibase; /* IDMA BD Base Address */
cyg_uint16 dcmr; /* DMA Channel Mode Register */
cyg_uint32 sapr; /* Source Internal Data Pointer */
cyg_uint32 dapr; /* Destination Internal Data Pointer */
cyg_uint16 ibptr; /* Buffer Descriptor Pointer */
cyg_uint16 write_sp; /* No description given in manual */
cyg_uint32 s_byte_c; /* Internal Source Byte Count */
cyg_uint32 d_byte_c; /* Internal Destination Byte Count */
cyg_uint32 s_state; /* Internal State */
cyg_uint32 itemp0; /* Temp Data Storage */
cyg_uint32 itemp1; /* Temp Data Storage */
cyg_uint32 itemp2; /* Temp Data Storage */
cyg_uint32 itemp3; /* Temp Data Storage */
cyg_uint32 sr_mem; /* Data Storage for Peripherial Write */
cyg_uint16 read_sp; /* No description given in manual */
cyg_uint16 nodesc0; /* Diff Between Source and Destination Residue*/
cyg_uint16 nodesc1; /* Temp Storage Address Pointer */
cyg_uint16 nodesc2; /* SR_MEM Byte Count */
cyg_uint32 d_state; /* Internal State */
};
/*--------------------------------------------------------------------------*/
/* RISC timer parameter RAM */
/*--------------------------------------------------------------------------*/
struct timer_pram
{
/*----------------------------*/
/* RISC timers parameter RAM */
/*----------------------------*/
cyg_uint16 tm_base; /* RISC timer table base adr */
cyg_uint16 tm_ptr; /* RISC timer table pointer */
cyg_uint16 r_tmr; /* RISC timer mode register */
cyg_uint16 r_tmv; /* RISC timer valid register */
cyg_uint32 tm_cmd; /* RISC timer cmd register */
cyg_uint32 tm_cnt; /* RISC timer internal cnt */
};
/*--------------------------------------------------------------------------*/
/* ROM Microcode parameter RAM */
/*--------------------------------------------------------------------------*/
struct ucode_pram
{
/*---------------------------*/
/* RISC ucode parameter RAM */
/*---------------------------*/
cyg_uint16 rev_num; /* Ucode Revision Number */
cyg_uint16 d_ptr; /* MISC Dump area pointer */
cyg_uint32 temp1; /* MISC Temp1 */
cyg_uint32 temp2; /* MISC Temp2 */
};
/*---------------------------------------------------------------------------*/
/* Example structuring of user data area of memory at 0x2000 (base of DPRAM) */
/* Note that this area can also be used by microcodes and the QMC channel */
/* specific parameter ram. */
/*---------------------------------------------------------------------------*/
struct user_data
{
volatile cyg_uint8 udata_bd_ucode[0x200]; /* user data bd's or Ucode (small) */
volatile cyg_uint8 udata_bd_ucode2[0x200]; /* user data bd's or Ucode (medium) */
volatile cyg_uint8 udata_bd_ucode3[0x400]; /* user data bd's or Ucode (large) */
volatile cyg_uint8 udata_bd[0x700]; /* user data bd's*/
volatile cyg_uint8 ucode_ext[0x100]; /* Ucode Extension ram*/
volatile cyg_uint8 RESERVED12[0x0c00]; /* Reserved area */
};
/***************************************************************************/
/* */
/* Definitions of Embedded PowerPC (EPPC) internal memory structures, */
/* including registers and dual-port RAM */
/* */
/***************************************************************************/
typedef struct eppc
{
/*-----------------------------------*/
/* BASE + 0x0000: INTERNAL REGISTERS */
/*-----------------------------------*/
/*-----*/
/* SIU */
/*-----*/
volatile cyg_uint32 siu_mcr; /* module configuration reg */
volatile cyg_uint32 siu_sypcr; /* System protection cnt */
cyg_uint8 RESERVED13[0x6];
volatile cyg_uint16 siu_swsr; /* sw service */
volatile cyg_uint32 siu_sipend; /* Interrupt pend reg */
volatile cyg_uint32 siu_simask; /* Interrupt mask reg */
volatile cyg_uint32 siu_siel; /* Interrupt edge level mask reg */
volatile cyg_uint32 siu_sivec; /* Interrupt vector */
volatile cyg_uint32 siu_tesr; /* Transfer error status */
volatile cyg_uint8 RESERVED14[0xc]; /* Reserved area */
volatile cyg_uint32 dma_sdcr; /* SDMA configuration reg */
cyg_uint8 RESERVED15[0x4c];
/*--------*/
/* PCMCIA */
/*--------*/
volatile cyg_uint32 pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
volatile cyg_uint32 pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
volatile cyg_uint32 pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
volatile cyg_uint32 pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
volatile cyg_uint32 pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
volatile cyg_uint32 pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
volatile cyg_uint32 pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
volatile cyg_uint32 pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
volatile cyg_uint32 pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
volatile cyg_uint32 pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
volatile cyg_uint32 pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
volatile cyg_uint32 pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
volatile cyg_uint32 pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
volatile cyg_uint32 pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
volatile cyg_uint32 pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
volatile cyg_uint32 pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
volatile cyg_uint8 RESERVED16[0x20]; /* Reserved area */
volatile cyg_uint32 pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
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