📄 quicc2_diag.c
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/*---------------------------------------*/
/* Program the Port Open-Drain Registers */
/*---------------------------------------*/
IMM->io_regs[PORT_C].podr &= 0xFFFDFFFF; /* CD/ pin 14 */
IMM->io_regs[PORT_D].podr &= 0xFFFFFFFC; /* TXD pin 30| RXD pin 31 */
}
/*---------------------------------------------------------------------------
*
* FUNCTION NAME: BDRxError
*
* DESCRIPTION:
*
* Return TRUE if Buffer Descriptor Status bd_cstatus indicates Receive
* Error; Return FALSE otherwise note Receive Errors are as follows:
*
* 0x80: DPLL Error (DE)
* 0x20: Length Violation (LG)
* 0x10: Non-Octet Aligned (NO)
* 0x8: Rx Abort Sequence (AB)
* 0x4: Rx CRC Error (CR)
* 0x2: Overrun (OV)
* 0x1: Carrier Detect Lost (CD)
*
* EXTERNAL EFFECTS: None
*
* PARAMETERS:
*
* bd_cstatus
*
* RETURNS: TRUE if there was an error and FALSE if there wasn't
*
*---------------------------------------------------------------------------*/
CYG_WORD16 BDRxError(CYG_WORD16 bd_cstatus)
{
if (bd_cstatus & BD_RX_ERROR)
return true;
else
return false;
} /* end BDRxError */
/*---------------------------------------------------------------------------
*
* FUNCTION NAME: SCC1Poll
*
* DESCRIPTION: Poll SCC1 RxBD and check to see if a character was received
*
* EXTERNAL EFFECT: NONE
*
* PARAMETERS: NONE
*
* RETURNS: A one if there is a character available in the receive buffer,
* else zero.
*
*--------------------------------------------------------------------------*/
cyg_uint8 SCC1Poll(void)
{
if(RxTxBD->RxBD.bd_cstatus & 0x8000)
{
return 0; /* character NOT available */
}
else
{
return 1; /* character IS available */
}
} /* END SCC1Poll */
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
void
cyg_hal_plf_serial_putc(cyg_uint8 ch)
#else
static void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch)
#endif
{
/*-----------------------------------*/
/* Loop until transmission completed */
/*-----------------------------------*/
#if 1
volatile CYG_WORD16 stat = 1;
while (stat){
stat = RxTxBD->TxBD.bd_cstatus & 0x8000;
}
#else
while (RxTxBD->TxBD.bd_cstatus & 0x8000);
#endif
/*------------*/
/* Store data */
/*------------*/
*(RxTxBD->TxBD.bd_addr) = ch;
RxTxBD->TxBD.bd_length = 1;
/*---------------*/
/* Set Ready bit */
/*---------------*/
RxTxBD->TxBD.bd_cstatus |= 0x8000;
}
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_bool retval;
if ( (retval = SCC1Poll() ) ){ /* Check BD status for Rx characters */
*ch = cyg_hal_plf_serial_getc(__ch_data);
}
return retval;
}
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
cyg_uint8
cyg_hal_plf_serial_getc(void)
#else
static cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
#endif
{
cyg_uint8 ch;
/*--------------------*/
/* Loop if RxBD empty */
/*--------------------*/
#if 1
volatile short stat = 1;
while (stat){
stat = RxTxBD->RxBD.bd_cstatus & 0x8000;
}
#else
while (RxTxBD->RxBD.bd_cstatus & 0x8000);
#endif
/*--------------*/
/* Receive data */
/*--------------*/
ch = *(RxTxBD->RxBD.bd_addr);
/*----------------------*/
/* Set Buffer Empty bit */
/*----------------------*/
RxTxBD->RxBD.bd_cstatus |= 0x8000;
return ch;
}
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
//CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
cyg_hal_plf_serial_putc(*__buf++);
#else
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
#endif
//CYGARC_HAL_RESTORE_GP();
}
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
while(__len-- > 0)
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
*__buf++ = cyg_hal_plf_serial_getc();
#else
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
#endif
CYGARC_HAL_RESTORE_GP();
}
cyg_int32 msec_timeout = 1000;
static cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count = msec_timeout * 10; // delay in .1 ms steps
cyg_bool res;
CYGARC_HAL_SAVE_GP();
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
int ret = 0;
cyg_uint32 regval;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
//HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_CPM_SMC1);
// For now, don't bother calling a macro, just do it here
// Bit 8 in the SIMR_L corresponds to SCC1
HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval);
regval |= 0x00800000;
HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval);
asm volatile ("ori %0, 0, 0x1234;" \
: /* No output */ \
: "I" (22)); /* %0 ==> r2 */
//RxTxBD->RxBD.bd_cstatus = 0xB000;
irq_state = 1;
//RED_LED_ON;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
//HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_CPM_SMC1);
HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval);
regval &= 0xFF7FFFFF;
HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval);
//RED_LED_OFF;
//RxTxBD->RxBD.bd_cstatus = 0xA000;
break;
case __COMMCTL_DBG_ISR_VECTOR:
//ret = CYGNUM_HAL_INTERRUPT_CPM_SMC1;
ret = CYGNUM_HAL_INTERRUPT_SCC1;
//ret = 0x01;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = msec_timeout;
msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
// EOF hal_aux.c
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