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📄 quicc2_diag.c

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   /*----------------------------------------------------------------------*/
   /* Issue Init RX & TX Parameters Command for SCC1. This command to the  */
   /* CP lets it know to reinitialize SCC1 with the new parameter RAM      */
   /* values. When the ENT/ENR bits are set below Hunt Mode will begin     */
   /* automatically.                                                       */
   /*----------------------------------------------------------------------*/

   while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 

   IMM->cpm_cpcr = SCC1_PAGE_SUBBLOCK |
                   CPCR_INIT_TX_RX_PARAMS |
                   CPCR_FLG;                 /* ISSUE COMMAND */

   while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 

   /*-------------------------------------------------------------*/
   /* Set the ENT/ENR bits in the GSMR -- Enable Transmit/Receive */
   /*-------------------------------------------------------------*/

    IMM->scc_regs[SCC1].gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR;
#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
    || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
#define PFADDED   
#ifdef PFADDED   
    // Fill out the control Character Table.  Make the first entry 
    // an end of table line. 
    // cc[0] = 0x4003 ==> reject if char = 0x3, write to RCCR
    IMM->pram.serials.scc_pram[SCC1].SpecificProtocol.u.cc[0] = 0x4003;
    {
        int i;
        for (i = 0; i < 8; i++){
            IMM->pram.serials.scc_pram[SCC1].SpecificProtocol.u.cc[i] = 0x8000;
        }
    }
    
    IMM->pram.serials.scc_pram[SCC1].SpecificProtocol.u.rccm  = 0xc000;
#endif
   /*-----------------------------------------*/
    /* Write to the SCCM mask register to enable an CCR interrupt*/
   /*-----------------------------------------*/
   IMM->scc_regs[SCC1].sccm = 0x1;

   /* Unmask the CPM SCC1 interrupt */
   HAL_READ_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval);
   regval |= 0x00800000;
   HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIMR_L, regval);

#endif
} /* end SCC1HInit() */


/*--------------------------------------------------------------------------
*
* FUNCTION NAME: ConfigSCC1Clock
*
* DESCRIPTION:
*
*  This function will configure SCC1 to utilize Baud Rate Generator #1. It 
*  will program the the baud rate generator and configure the SMXSCR 
*  register in the CPM Mux block to route the clock to SCC1. SCC2, SCC3, and
*  SCC4 are also programmed to assume Baud Rate Generator #1, #2, and #3 
*  respectively to be routed to them. There was no special reason for doing
*  this; The bit values needed to be programmed to something.
*
*
* EXTERNAL EFFECTS: BRGC1 and CMXSCR
*
* PARAMETERS:  
*
* RETURNS: Nothing
*
*--------------------------------------------------------------------------*/

void  ConfigSCC1Clock()

{
    /* FIXME --- This picture is not accurate */
   /*----------------------------------------------------------------------*/
   /* Initialize Baud Rate Generator #1 to generate a 9600 clock. The      */
   /* source of the clock starts with the input clock that is generated    */
   /* external to the MPC8260 by a clock generator. This clock is then     */
   /* fed to the CPM PLL where it is multiplied up and the output freq-    */
   /* uency is determined by the MODCLK_HI bits in the Hard Reset Config-  */
   /* uration Word and MODCK pins on the MPC8260. This output is fed to a  */
   /* general purpose Baud Rate Generator Divider that services all 8 baud */
   /* rate generators. From the output of this divider the the clock goes  */
   /* to the baud rate generator circuitry where, in this case, BRGCLK is  */
   /* selected to be BRGO1 (the output clock). This frequency is deter-    */
   /* mined by a Divide by 1 or 16 divider and then a 12 bit Prescaler     */
   /* divider. the clock then goes to the CPM Mux where BRG1 is selected   */
   /* to be TCLK and RCLK to SCC1. This is accomplished by programming the */
   /* CMXSCR register. TCLK and RCLK are then routed to the SCC1 DPLL      */
   /* circuitry at 9600 baud where the DPLL will be programmed to multiply */
   /* the frequency by X16 for UART over-sampling. Here a diagram and the  */
   /* programming:                                                         */
   /*                                                                      */
   /* ----------    ---------         ---------------------                */
   /* |External|    |MPC8260| 132 Mhz |General Purpose    | 16.5 Mhz       */
   /* |Clk Gen |----|CPM PLL|---------|Baud Rate Generator|--------->|     */
   /* |66 Mhz  |    |Block  |         |Divider [/8] (SCCR)|          |     */
   /* ----------    ---------         ---------------------          |     */
   /*                                                                |     */
   /* |<-------------------------------------------------------------|     */
   /* |                                                                    */
   /* |   ------------------------              -------------------        */
   /* |-->|Divide by 1 or 16 in  | 1.03125 Mhz  |12 Bit Prescaler  | BRG01 */
   /*     |Baud Rate Generator   |------------->|in Baud Rate Gen. |--|    */
   /*     |Block [/16 selected]  |              |Block [107(0x6B)  |  |    */
   /*     |(BRGC1 Programmed)    |              |(BRGC1 Programmed)|  |    */
   /*     ------------------------              --------------------  |    */
   /*                                                                 |    */
   /* |<--------------------------------------------------------------|    */
   /* |                                                                    */
   /* |            -------------- TCLK  ----------                         */                     
   /* | 9.638 Khz  |   CPM Mux  |------>| SCC1   |----> TCLK*16 }*16 for   */
   /* |----------->|  (CMXSCR)  | RCLK  | DPLL   |              }over-     */
   /*              |(Programmed)|------>| *16    |----> RCLK*16 }sampling  */
   /*              --------------       |(GSMR_L)|                         */
   /*                                   ----------                         */
   /*                                                                      */
   /* SCCR was programmed in init8260.s. BRGC1,CMXSCR will be programmed   */
   /* in this function. GSMR_L will be programmed in InitSCC1Uart().       */   
   /*                                                                      */
   /*----------------------------------------------------------------------*/

   /*----------------------------------------------------------------------*/
   /* Program Baud Rate Generator Configuration #1 Register (BRGC1).       */
   /*                                                                      */
   /* - Bits 0-13 are reserved. Set to 0.                                  */
   /*                                                                      */
   /* - RST (Reset BRG) = 0 = Enable the BRG                               */
   /*                                                                      */
   /* - EN (Enable BRG Count) = 1 = Enable clocks to the BRG               */
   /*                                                                      */
   /* - EXTC (External Clock Source) = 00 =                                */
   /*                                                                      */
   /*    The BRG input clock comes from the BRGCLK                         */
   /*                                                                      */
   /* - ATB (AutoBaud) = 0 = Normal operation of the BRG.                  */
   /*                                                                      */
   /* - CD (Clock Divider) = 0x6C = 108 decimal =                          */
   /*                                                                      */
   /*    The input frequency is 1.03125 Mhz Dividing it by 107 will give   */
   /*    9.638 Khz. However 1 must be added to the count value because it  */
   /*    counts down to 0. So the programmed value is 108.                 */
   /*                                                                      */
  /* PF edit - changed CD = 0x1A = 26 ==> baud rate of 4 * 9600 = 38400    */
   /* - DIV16 (Divide-by-16) = 0 = divide by 1.                           */
   /*----------------------------------------------------------------------*/

  //     IMM->brgs_brgc1 = 0x000100D6;   
  //IMM->brgs_brgc1 = 0x00010034; /* Attempt to get 38400 baud */   
  // IMM->brgs_brgc1 = 0x00010022; /* Attempt to get 57600 baud */   
  //IMM->brgs_brgc1 = 0x00010010; /* Attempt to get 115200 baud */   
  IMM->brgs_brgc1 = 0x00010000 | (UART_BIT_RATE(UART_BAUD_RATE) << 1);

   /*----------------------------------------------------------------------*/
   /* Program the CMX SCC Route Register (CMXSCR).                         */
   /*                                                                      */
   /* - GR1 (Grant support of SCC1) = 0 =                                  */
   /*                                                                      */
   /*    SCC1 transmitter does not support the grant mechanism. The grant  */
   /*    is always asserted internally.                                    */
   /*                                                                      */
   /* - SC1 (SCC1 connection) = 0                                          */
   /*                                                                      */
   /*    SCC1 is not connected to the TSA of the SIs but is connected      */
   /*    directly to the NMSIx pins.                                       */
   /*                                                                      */
   /* - RS1CS (Receive SCC1 or clock source) = 000 =                       */
   /*                                                                      */
   /*    SCC1 receive clock is BRG1.                                       */
   /*                                                                      */
   /* - TS1CS (Transmit SCC1 clock source) = 000 =                         */
   /*                                                                      */
   /*    SCC1 transmit clock is BRG1.                                      */
   /*                                                                      */
   /* - GR2 (Grant support of SCC2) = 0 =                                  */
   /*                                                                      */
   /*    SCC1 transmitter does not support the grant mechanism. The grant  */
   /*    is always asserted internally.                                    */
   /*                                                                      */
   /* - SC2 (SCC2 connection) = 0                                          */
   /*                                                                      */
   /*    SCC2 is not connected to the TSA of the SIs but is connected      */
   /*    directly to the NMSIx pins.                                       */
   /*                                                                      */
   /* - RS2CS (Receive SCC2 or clock source) = 001 =                       */
   /*                                                                      */
   /*    SCC1 receive clock is BRG2.                                       */
   /*                                                                      */
   /* - TS2CS (Transmit SCC2 clock source) = 001 =                         */
   /*                                                                      */
   /*    SCC2 transmit clock is BRG2.                                      */
   /*                                                                      */
   /* - GR3 (Grant support of SCC3) = 0 =                                  */
   /*                                                                      */
   /*    SCC3 transmitter does not support the grant mechanism. The grant  */
   /*    is always asserted internally.                                    */
   /*                                                                      */
   /* - SC3 (SCC3 connection) = 0                                          */
   /*                                                                      */
   /*    SCC3 is not connected to the TSA of the SIs but is connected      */
   /*    directly to the NMSIx pins.                                       */
   /*                                                                      */
   /* - RS3CS (Receive SCC3 or clock source) = 010 =                       */
   /*                                                                      */
   /*    SCC3 receive clock is BRG3.                                       */
   /*                                                                      */
   /* - TS3CS (Transmit SCC3 clock source) = 010 =                         */
   /*                                                                      */
   /*    SCC3 transmit clock is BRG3.                                      */
   /*                                                                      */
   /* - GR4 (Grant support of SCC4) = 0 =                                  */
   /*                                                                      */
   /*    SCC4 transmitter does not support the grant mechanism. The grant  */
   /*    is always asserted internally.                                    */
   /*                                                                      */
   /* - SC4 (SCC4 connection) = 0                                          */
   /*                                                                      */
   /*    SCC4 is not connected to the TSA of the SIs but is connected      */
   /*    directly to the NMSIx pins.                                       */
   /*                                                                      */
   /* - RS4CS (Receive SCC4 or clock source) = 011 =                       */
   /*                                                                      */
   /*    SCC4 receive clock is BRG4.                                       */
   /*                                                                      */
   /* - TS4CS (Transmit SCC4 clock source) = 011 =                         */
   /*                                                                      */
   /*    SCC4 transmit clock is BRG4.                                      */
   /*                                                                      */
   /*----------------------------------------------------------------------*/

   IMM->cpm_mux_cmxscr = 0x0009121B;  

} /* end of ConfigSCC1Clock() */



/*--------------------------------------------------------------------------
*
* FUNCTION NAME: InitParallelPorts
*
* DESCRIPTION:
*
*  This function programs the parallel port configuration registers to 
*  utilize the pins required for proper SCC1 operation. The pins programmed 
*  here are TxD and RxD for SCC1 and CD1 for SCC1.
*
* EXTERNAL EFFECTS: Parallel Port C and D Configuration Registers
*
* PARAMETERS:  
*
* RETURNS: Nothing
*
*--------------------------------------------------------------------------*/

void InitParallelPorts()

{
   /*--------------------------------------------*/
	/* Program the Port Special Options Registers */
   /*--------------------------------------------*/

	IMM->io_regs[PORT_C].psor &= 0xFFFDFFFF; /* CD/ pin 14 */
	IMM->io_regs[PORT_D].psor &= 0xFFFFFFFC; /* clear first */
	IMM->io_regs[PORT_D].psor |= 0x00000002; /* TXD pin 30| RXD pin 31 */

   /*-------------------------------------------*/
	/* Program the Port Pin Assignment Registers */
   /*-------------------------------------------*/

	IMM->io_regs[PORT_C].ppar |= 0x00020000;   /* CD/ pin 14 */
	IMM->io_regs[PORT_D].ppar |= 0x00000003;   /* TXD pin 30| RXD pin 31 */

   /*-------------------------------------------*/
	/* Program the Port Data Direction Registers */
   /*-------------------------------------------*/

	IMM->io_regs[PORT_C].pdir &= 0xFFFDFFFF;   /* CD/ pin 14 */
	IMM->io_regs[PORT_D].pdir &= 0xFFFFFFFC;   /* clear first */
	IMM->io_regs[PORT_D].pdir |= 0x00000002;   /* TXD pin 30| RXD pin 31 */

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