quicc2_diag.c

开放源码实时操作系统源码.

//=============================================================================
//
//      quicc2_diag.c
//
//      HAL diagnostic I/O support routines for MPC8260/QUICC2
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   hmt
// Contributors:hmt, gthomas
// Date:        1999-06-08
// Purpose:     HAL diagnostics I/O support
// Description: 
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>
#include <cyg/hal/hal_mem.h>            // HAL memory definitions
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_if.h>             // hal_if_init
#include <cyg/hal/hal_io.h>             // hal_if_init
#include <cyg/hal/hal_misc.h>           // cyg_hal_is_break

#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
// Added by WPD
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/var_intr.h>
#include <cyg/hal/mpc8260.h>            // Needed for IMMR structure

// For Baud Rate Calculation, see MPC8260 PowerQUICC II User's Manual
// 16.3 UART Baud Rate Examples, page 16-5.
// BRGCx[DIV16]  = 0 ==> value of 1 (Prescale divider)
// BRGCx[EXTC]   = 16.667 MHz (Baud Rate generator input clock)
// GSMRx_L[xDCR] = 16 (Sampling Rate)
// UART_CLK_DIV + 1 = 
//       BRGCx[EXTC] / (BRGCx[DIV16] * UART_BAUD_RATE * GSMRx_L[xDCR])
// UART_CLK_DIV = ((66.667 MHz / 4) / (UART_BAUD_RATE * 16)) - 1
// UART_CLK_DIV = ((66.667 MHz ) / (UART_BAUD_RATE * 64)) - 1
// UART_CLK_DIV = ((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000 ) 
//                / (UART_BAUD_RATE * 64)) (Calculation will truncate, so 
//                                         lose the -1 )
#define UART_BIT_RATE(n) \
    (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000))/(n * 64))
#define UART_BAUD_RATE CYGNUM_HAL_DIAG_BAUD


/***********************/
/* Global Declarations */
/***********************/
//#define USE_SMC1

volatile t_PQ2IMM  *IMM;   /* IMM base pointer */
volatile BDRINGS *RxTxBD;  /* buffer descriptors base pointer */
volatile LB *SCC1Buffers;  /* SCC1 base pointers */

#define SMC1_PRAM   0x04703800
#define BD_RX_ERROR 0xBF    /* Mask for set of Receive Buffer Errors,
                               including: DE, LG, NO, AB, CR, OV, CD */

/*---------------------*/
/* Function Prototypes */
/*---------------------*/

static void  InitSCC1Uart(void);
static void  ConfigSCC1Clock(void);
static void  InitParallelPorts(void);
static cyg_uint8 SCC1Poll(void);
static void  InitBDs(void);

static cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data);

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch);

static cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch);

static void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch);

static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
                         cyg_uint32 __len);
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len);

static void
cyg_hal_plf_serial_init_channel(void);

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data);

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...);

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    t_PQ2IMM  *immr = (t_PQ2IMM*) __ch_data;
    struct cp_bufdesc *bd;
    char ch;
    int res = 0;
    cyg_uint32 regval;

    CYGARC_HAL_SAVE_GP();
    //GREEN_LED_ON;
/*
    dbg_values[3]++;
    dbg_values[10+dbg_values[3]] = 
        RxTxBD->RxBD.bd_cstatus
        | (immr->scc_regs[SCC1].scce<<16);
*/
    *__ctrlc = 0;
    if (immr->scc_regs[SCC1].scce & 0x0001) {

        // Clear the event by writing a "1" to the prpoper bit.
        immr->scc_regs[SCC1].scce = 0x0001;

        if((RxTxBD->RxBD.bd_cstatus  &  0x8000) == 0){
            ch = *(RxTxBD->RxBD.bd_addr);
            /*----------------------*/
            /* Set Buffer Empty bit */
            /*----------------------*/
            //dbg_values[10+dbg_values[3]] = __vector | 0xffff0000;
            //dbg_values[10+dbg_values[3]] |= ch << 8;
    
            RxTxBD->RxBD.bd_cstatus |= 0x8000;   

            if( cyg_hal_is_break( &ch , 1 ) ){
                //GREEN_LED_ON;
              *__ctrlc = 1;
              //dbg_values[7] = immr->ic_sivec;              
            }
        }
        // Interrupt handled. Acknowledge it.
        //eppc->cpmi_cisr = 0x10;
        // Clear interrupt in SIPNR_L by writing a one to bit 8 (0x800000)
        HAL_READ_UINT32(  ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIPNR_L,
                         regval);
        regval |= 0x00800000;
        HAL_WRITE_UINT32( ((char *) IMM) + 0x10000 + CYGARC_REG_IMM_SIPNR_L,
                          regval);

        res = CYG_ISR_HANDLED;
    }

    //GREEN_LED_OFF;
    CYGARC_HAL_RESTORE_GP();
    return res;
}

/* Early initialization of comm channels. Must not rely
 * on interrupts, yet. Interrupt operation can be enabled
 * in _bsp_board_init().
 */
void
cyg_hal_plf_serial_init(void)
{
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
    hal_virtual_comm_table_t* comm;
    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);

    static int init = 0;  // It's wrong to do this more than once
    if (init) return;
    init++;

    // init_channel sets the global *IMM == 0x04700000, the base of the
    // Internal Memory map for the MPC8260
    cyg_hal_plf_serial_init_channel();

    // Setup procs in the vector table

    // Set channel 0
    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);// Should be configurable!
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
    CYGACC_COMM_IF_CH_DATA_SET(*comm, IMM);
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);

    // Restore original console
    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);

#else // No CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
    static int init = 0;  // It's wrong to do this more than once
    if (init) return;
    init++;

    cyg_hal_plf_serial_init_channel();
#endif
}

static void
cyg_hal_plf_serial_init_channel(void)
{
    /* We will assume here that the IMMR has been programmed such that
     * the internal Memory Map starts at 0x04700000.  Initialization
     * should have done that setup.
     */

    IMM =  (t_PQ2IMM *)0x04700000;  /* MPC8260 internal register map  */

    /*----------------------------------------------------------------------*/  
    /* Get a pointer to the BD area on DP RAM. The buffer descriptors (BDs) */
    /* and the Rx/Tx data buffers will be located right after SCC1's para-  */
    /* meter RAM area because only 2 BDs and 2 data buffers are being used  */
    /* for this port and SCC1 only uses 64 bytes of it's allotted 256 for   */
    /* it's parameter ram. One BD and one data buffer each for transmit and */
    /* receive will be used. This buffer descriptor area will take up 16    */
    /* bytes.                                                               */
    /*----------------------------------------------------------------------*/  
      

    RxTxBD = (BDRINGS *) 0x04708070;
    //    (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + 72);  

    //RxTxBD = (BDRINGS *)
    //    (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + 72);  

    /*-------------------------------------------------------------------*/
    /* Establish the buffer pool in Dual Port RAM. We do this because the*/
    /* pool size is only 2 bytes (1 for Rx and 1 for Tx) and to avoid    */
    /* disabling data cache for the memory region where BufferPool would */
    /* reside. The CPM does not recognize data in buffer pools once it   */
    /* been cached. It's acesses are direct through DMA to external      */
    /* memory.                                                           */
    /*-------------------------------------------------------------------*/

    //SCC1Buffers = (LB *)
    //    (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1])) + 96); 

    SCC1Buffers = (LB *) 0x04708090;
    //    (((CYG_WORD)&(IMM->pram.serials.scc_pram[SCC1]))
    //     + 72 + 14); 

   /*----------------------------------------*/
   /* Initialize SCC1 and buffer descriptors */
   /*----------------------------------------*/