📄 sed1356_16bit.h
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// 0 = Passive Mono, 1 = Passive Color
#define SED1356_PANEL_TYPE_DUAL BIT1
// 0 = Passive Single, 1 = Passive Dual
#define SED1356_PANEL_TYPE_TFT BIT0
// 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares)
// SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE,
// SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE
#define SED1356_PULSE_POL_HIGH BIT7
// 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low
#define SED1356_PULSE_POL_LOW 0x00
// 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low
#define SED1356_PULSE_WID(_x_) (_x_ & 0x0f)
// Pulse Width in Pixels
// SED1356_LCD_DISP_MODE_and_MISC - even
#define SED1356_LCD_DISP_BLANK BIT7
// 1 = Blank LCD Display
#define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4)
// Used with SED1356_REG_DISP_MODE Bit 6
#define SED1356_LCD_DISP_SWIV_90 (0x00 << 4)
#define SED1356_LCD_DISP_SWIV_180 (0x01 << 4)
#define SED1356_LCD_DISP_SWIV_270 (0x01 << 4)
#define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4)
#define SED1356_LCD_DISP_16BPP 0x05
// Bit Per Pixel Selection
#define SED1356_LCD_DISP_15BPP 0x04
#define SED1356_LCD_DISP_8BPP 0x03
#define SED1356_LCD_DISP_4BPP 0x02
#define SED1356_LCD_DISP_BPP_MASK 0x07
// SED1356_LCD_DISP_MODE_and_MISC - odd
#define SED1356_LCD_MISC_DITH BIT1 << 8
// 1 = Dither Disable, Passive Panel Only
#define SED1356_LCD_MISC_DUAL BIT0 << 8
// 1 = Dual Panel Disable, Passive Panel Only
// SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd
#define SED1356_CRT_OUT_CHROM BIT5 << 8
// 1 = TV Chrominance Filter Enable
#define SED1356_CRT_OUT_LUM BIT4 << 8
// 1 = TV Luminance Filter Enable
#define SED1356_CRT_OUT_DAC_LVL BIT3 << 8
// 1 = 4.6ma IREF, 0 = 9.2 IREF
#define SED1356_CRT_OUT_SVIDEO BIT1 << 8
// 1 = S-Video Output, 0 = Composite Video Output
#define SED1356_CRT_OUT_PAL BIT0 << 8
// 1 = PAL Format Output, 0 = NTSC Format Output
// SED1356_REG_CRT_DISP_MODE
#define SED1356_CRT_DISP_BLANK BIT7
// 1 = Blank CRT Display
#define SED1356_CRT_DISP_16BPP 0x05
// Bit Per Pixel Selection
#define SED1356_CRT_DISP_15BPP 0x04
#define SED1356_CRT_DISP_8BPP 0x03
#define SED1356_CRT_DISP_4BPP 0x02
#define SED1356_CRT_DISP_BPP_MASK 0x07
// SED1356_DISP_MODE
#define SED1356_DISP_SWIV_NORM (0x00 << 6)
// Used with SED1356_LCD_DISP_MODE Bit 4
#define SED1356_DISP_SWIV_90 (0x01 << 6)
#define SED1356_DISP_SWIV_180 (0x00 << 6)
#define SED1356_DISP_SWIV_270 (0x01 << 6)
#define SED1356_DISP_MODE_OFF 0x00
// All Displays Off
#define SED1356_DISP_MODE_LCD 0x01
// LCD Only
#define SED1356_DISP_MODE_CRT 0x02
// CRT Only
#define SED1356_DISP_MODE_LCD_CRT 0x03
// Simultaneous LCD and CRT
#define SED1356_DISP_MODE_TV 0x04
// TV Only, Flicker Filter Off
#define SED1356_DISP_MODE_TV_LCD 0x05
// Simultaneous LCD and TV, Flicker Filter Off
#define SED1356_DISP_MODE_TV_FLICK 0x06
// TV Only, Flicker Filter On
#define SED1356_DISP_MODE_TV_LCD_FLICK 0x07
// Simultaneous LCD and TV, Flicker Filter On
// SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT
#define SED1356_PWR_PCLK BIT1
// SED1356_REG_PWR_STAT only
#define SED1356_PWR_MCLK BIT0
// SED1356_REG_VER_NONDISP
#define SED1356_VER_NONDISP BIT7
// vertical retrace status 1 = in retrace
// Display size defines
#define PIXELS_PER_ROW 640
#define PIXELS_PER_COL 480
#define BYTES_PER_PIXEL 2
#define COLS_PER_SCREEN 80
#define ROWS_PER_SCREEN 30
// 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the
// LCD Interface, while the LSB of GREEN is loaded as 0
#define RED_SUBPIXEL(n) ((n & 0x1f) << 11)
#define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5)
#define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0)
// define a simple VGA style 16-color pallette
#define LU_BLACK (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
#define LU_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f))
#define LU_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00))
#define LU_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f))
#define LU_RED (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
#define LU_VIOLET (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f))
#define LU_YELLOW (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00))
#define LU_GREY (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f))
#define LU_WHITE (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17))
#define LU_BRT_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f))
#define LU_BRT_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00))
#define LU_BRT_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f))
#define LU_BRT_RED (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00))
#define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f))
#define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00))
#define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f))
static const ushort vga_lookup[] = {
LU_BLACK,
// 0
LU_BLUE,
// 1
LU_GREEN,
// 2
LU_CYAN,
// 3
LU_RED,
// 4
LU_GREY,
// 5
LU_VIOLET,
// 6
LU_YELLOW,
// 7
LU_WHITE,
// 8
LU_BRT_BLUE,
// 9
LU_BRT_GREEN,
// 10
LU_BRT_CYAN,
// 11
LU_BRT_RED,
// 12
LU_BRT_VIOLET,
// 13
LU_BRT_YELLOW,
// 14
LU_BRT_WHITE
// 15
};
// default foreground and background colors
#define SED_BG_DEF 1
#define SED_FG_DEF 14
// Vertical and Horizontal Pulse, Start and Non-Display values vary depending
// upon the mode. The following section gives some insight into how the
// values are arrived at.
// ms = milliseconds, us = microseconds, ns = nanoseconds
// Mhz = Megaherz, Khz = Kiloherz, Hz = Herz
//
// ***************************************************************************************************
// CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns)
// ***************************************************************************************************
//
// CRT MODE HORIZONTAL TIMING PARAMETERS
//
// |<-------Tha------->|
// |___________________| ______
// Display Enable _____________________| |____________________|
// | |
// Horizontal Pulse __ ________|___________________|________ __________
// |_________| | | |________|
// |<- Thp ->| | | |
// | |<-Thbp->| | |
// | |<-Thfp->|
// |<----------------------Tht-------------------->|
//
// Tha - Active Display Time = 640 pixels
// Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels
// Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels
// Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels
// Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz
//
// Correlation between horizontal timing parameters and SED registers
#define SED_HOR_PULSE_WIDTH_CRT 0x07
// Horizontal Pulse Width Register = (Thp/8) - 1
#define SED_HOR_PULSE_START_CRT 0x02
// Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1
#define SED_HOR_NONDISP_CRT 0x17
// Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1
//
// CRT MODE VERTICAL TIMING PARAMTERS
//
// |<-------Tva------->|
// |___________________| ______
// Display Enable _____________________| |_____________________|
// | |
// Vertical Pulse __ ________|___________________|________ __________
// |_________| | | |________|
// |<- Tvp ->| | | |
// | |<-Tvbp->| | |
// | |<-Tvfp->|
// |<----------------------Tvt-------------------->|
//
// Tva - Active Display Time = 480 lines
// Tvp - Vertical Pulse = 3 lines
// Tvfp - Vertical Front Porch = 9 lines
// Tvbp - Vertical Back Porch = 28 lines
// Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz
//
// Correlation between vertical timing parameters and SED registers
#define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register = Tvp - 1
#define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1
#define SED_VER_NONDISP_CRT 0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
//
// ***************************************************************************************************
// DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns)
// ***************************************************************************************************
//
// LCD MODE HORIZONTAL TIMING PARAMTERS
//
// |<-------Tha------->|
// |___________________| ______
// Display Enable _____________________| |____________________|
// | |
// Horizontal Pulse __ ________|___________________|________ __________
// |_________| | | |________|
// |<- Thp ->| | | |
// | |<-Thbp->| | |
// | |<-Thfp->|
// |<----------------------Tht-------------------->|
//
// Tha - Active Display Time = 640 pixels
// Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels
// Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels
// Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels
// Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz
//
// Correlation between horizontal timing parameters and SED registers
#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1
#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2
#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1
//
// LCD MODE VERTICAL TIMING PARAMTERS
//
// |<-------Tva------->|
// |___________________| ______
// Display Enable _____________________| |_____________________|
// | |
// Vertical Pulse __ ________|___________________|________ __________
// |_________| | | |________|
// |<- Tvp ->| | | |
// | |<-Tvbp->| | |
// | |<-Tvfp->|
// |<----------------------Tvt-------------------->|
//
// Tva - Active Display Time = 480 lines
// Tvp - Vertical Pulse = 2 lines
// Tvfp - Vertical Front Porch = 10 lines
// Tvbp - Vertical Backporch = 33 lines
// Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz
//
// Correlation between vertical timing parameters and SED registers
#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1
#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1
#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
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