📄 var_intr.h
字号:
#ifndef CYGONCE_VAR_INTR_H
#define CYGONCE_VAR_INTR_H
//=============================================================================
//
// var_intr.h
//
// Variant HAL interrupt and clock support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors:Bob Koninckx
// Date: 2001-12-15
// Purpose: Variant interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock on the MPC5xx variant CPUs.
// Usage: Is included via the architecture interrupt header:
// #include <cyg/hal/hal_intr.h>
// ...
//
//####DESCRIPTIONEND####
//
//=============================================================================
#include <pkgconf/hal.h>
#include <cyg/hal/plf_intr.h>
#include <cyg/infra/cyg_type.h> // types
#include <cyg/hal/ppc_regs.h> // register definitions
#include <cyg/hal/hal_io.h> // io macros
#include <cyg/infra/cyg_ass.h> // CYG_FAIL
//-----------------------------------------------------------------------------
// Special IMB3 arbitration code
typedef struct t_hal_mpc5xx_arbitration_data {
cyg_uint32 priority;
CYG_ADDRWORD data;
cyg_uint32 (* arbiter)(CYG_ADDRWORD, CYG_ADDRWORD);
void * reserved;
} hal_mpc5xx_arbitration_data;
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data *adata);
externC hal_mpc5xx_arbitration_data *
hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority);
//-----------------------------------------------------------------------------
// Exception vectors.
// Additional exceptions on the MPC5xx CPUs
#define CYGNUM_HAL_VECTOR_RESERVED_F 15
#define CYGNUM_HAL_VECTOR_SW_EMUL 16
#define CYGNUM_HAL_VECTOR_RESERVED_11 17
#define CYGNUM_HAL_VECTOR_RESERVED_12 18
#define CYGNUM_HAL_VECTOR_ITLB_ERROR 19
#define CYGNUM_HAL_VECTOR_DTLB_ERROR 20
#define CYGNUM_HAL_VECTOR_RESERVED_15 21
#define CYGNUM_HAL_VECTOR_RESERVED_16 22
#define CYGNUM_HAL_VECTOR_RESERVED_17 23
#define CYGNUM_HAL_VECTOR_RESERVED_18 24
#define CYGNUM_HAL_VECTOR_RESERVED_19 25
#define CYGNUM_HAL_VECTOR_RESERVED_1A 26
#define CYGNUM_HAL_VECTOR_RESERVED_1B 27
#define CYGNUM_HAL_VECTOR_DATA_BP 28
#define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29
#define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30
#define CYGNUM_HAL_VECTOR_NMI 31
#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI
// These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()
#define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
#define CYGNUM_HAL_EXCEPTION_RESERVED_3 CYGNUM_HAL_VECTOR_RESERVED_3
#define CYGNUM_HAL_EXCEPTION_RESERVED_4 CYGNUM_HAL_VECTOR_RESERVED_4
#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ALIGNMENT
#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
#define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A
#define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B
#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
#define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE
#define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST
#define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F
#define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL
#define CYGNUM_HAL_EXCEPTION_RESERVED_11 CYGNUM_HAL_VECTOR_RESERVED_11
#define CYGNUM_HAL_EXCEPTION_RESERVED_12 CYGNUM_HAL_VECTOR_RESERVED_12
#define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_ITLB_ERROR
#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_DTLB_ERROR
#define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15
#define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16
#define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17
#define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18
#define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19
#define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A
#define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B
#define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP
#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP
#define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP
#define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI
// decoded exception vectors (decoded program exception)
#define CYGNUM_HAL_EXCEPTION_TRAP (-1)
#define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2)
#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3)
#define CYGNUM_HAL_EXCEPTION_FPU (-4)
#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0
#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI
#define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
//-----------------------------------------------------------------------------
// Interrupts
// The first level of external interrupts
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1
#define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3
#define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5
#define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7
#define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9
#define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11
#define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13
#define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15
#define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16
// Further decoded interrupts
#define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17 // Time base reference A
#define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18 // Time base reference B
#define CYGNUM_HAL_INTERRUPT_SIU_PIT 19 // Periodic interrupt timer
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20 // Real time clock once per second
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21 // Real time clock alarm
#define CYGNUM_HAL_INTERRUPT_SIU_COL 22 // Change of lock of the PLL
// Even further decoded interrupts
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 23 // QUADCA queue 1 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1 24 // QUADCA queue 1 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2 25 // QUADCA queue 2 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2 26 // QUADCA queue 2 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1 27 // QUADCB queue 1 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1 28 // QUADCB queue 1 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2 29 // QUADCB queue 2 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2 30 // QUADCB queue 2 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX 31 // SCI 0 transmit
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC 32 // SCI 0 transmit complete
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX 33 // SCI 0 receiver full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE 34 // SCI 0 idle line detected
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX 35 // SCI 1 transmit
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC 36 // SCI 1 transmit complete
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX 37 // SCI 1 receiver full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE 38 // SCI 1 idle line detected
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF 39 // SCI 1 RX Queue top half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF 40 // SCI 1 RX Queue bottom half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE 41 // SCI 1 TX Queue top half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE 42 // SCI 1 TX Queue bottom half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI 43 // SPI finished
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF 44 // SPI Mode fault
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA 45 // SPI Halt Acknowledge
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF 46 // TOUCANA buss off
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR 47 // TOUCANA error
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU 48 // TOUCANA wake up
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0 49 // TOUCANA buffer 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1 50 // TOUCANA buffer 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2 51 // TOUCANA buffer 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3 52 // TOUCANA buffer 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4 53 // TOUCANA buffer 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5 54 // TOUCANA buffer 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6 55 // TOUCANA buffer 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7 56 // TOUCANA buffer 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8 57 // TOUCANA buffer 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9 58 // TOUCANA buffer 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10 59 // TOUCANA buffer 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11 60 // TOUCANA buffer 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12 61 // TOUCANA buffer 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13 62 // TOUCANA buffer 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14 63 // TOUCANA buffer 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15 64 // TOUCANA buffer 15
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF 65 // TOUCANB buss off
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR 66 // TOUCANB error
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU 67 // TOUCANB wake up
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0 68 // TOUCANB buffer 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1 69 // TOUCANB buffer 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2 70 // TOUCANB buffer 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3 71 // TOUCANB buffer 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4 72 // TOUCANB buffer 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5 73 // TOUCANB buffer 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6 74 // TOUCANB buffer 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7 75 // TOUCANB buffer 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8 76 // TOUCANB buffer 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9 77 // TOUCANB buffer 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10 78 // TOUCANB buffer 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11 79 // TOUCANB buffer 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12 80 // TOUCANB buffer 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13 81 // TOUCANB buffer 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14 82 // TOUCANB buffer 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15 83 // TOUCANB buffer 15
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0 84 // TPU A channel 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1 85 // TPU A channel 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2 86 // TPU A channel 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3 87 // TPU A channel 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4 88 // TPU A channel 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5 89 // TPU A channel 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6 90 // TPU A channel 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7 91 // TPU A channel 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8 92 // TPU A channel 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9 93 // TPU A channel 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10 94 // TPU A channel 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11 95 // TPU A channel 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12 96 // TPU A channel 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13 97 // TPU A channel 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14 98 // TPU A channel 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15 99 // TPU A channel 15
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0 100 // TPU B channel 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1 101 // TPU B channel 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2 102 // TPU B channel 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3 103 // TPU B channel 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4 104 // TPU B channel 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5 105 // TPU B channel 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6 106 // TPU B channel 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7 107 // TPU B channel 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8 108 // TPU B channel 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9 109 // TPU B channel 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10 110 // TPU B channel 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11 111 // TPU B channel 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12 112 // TPU B channel 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13 113 // TPU B channel 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14 114 // TPU B channel 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15 115 // TPU B channel 15
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0 116 // MIOS PWM0
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1 117 // MIOS PWM1
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2 118 // MIOS PWM2
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3 119 // MIOS PWM3
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6 120 // MIOS MCSM6
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11 121 // MIOS MDASM11
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12 122 // MIOS MDASM12
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13 123 // MIOS MDASM13
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14 124 // MIOS MDASM14
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15 125 // MIOS MDASM15
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16 126 // MIOS PWM16
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17 127 // MIOS PWM17
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18 128 // MIOS PWM18
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19 129 // MIOS PWM19
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22 130 // MIOS MCSM22
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27 131 // MIOS MDASM27
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28 132 // MIOS MDASM28
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29 133 // MIOS MDASM29
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30 134 // MIOS MDASM30
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31 135 // MIOS MDASM31
#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31
#define CYGARC_SIU_PRIORITY_HIGH 7 // Maximum interrupt priority on SIU
#define CYGARC_SIU_PRIORITY_LOW 0 // Minimum interrupt priority on SIU
#define CYGARC_IMB3_PRIORITY_HIGH 31 // Maximum interrupt priority on IMB3
#define CYGARC_IMB3_PRIORITY_LOW 0 // Minimum interrupt priority on IMB3
//--------------------------------------------------------------------------
// Interrupt controller access
static __inline__ void
cyg_hal_interrupt_mask ( cyg_uint32 vector )
{
switch (vector) {
case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
{
// SIU interrupt vectors
cyg_uint32 simask;
HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRM0)
>> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_TB_A :
{
// TimeBase A interrupt
cyg_uint16 tbscr;
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_TB_B :
{
// TimeBase B interrupt
cyg_uint16 tbscr;
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_PIT:
{
// Periodic Interrupt
cyg_uint16 piscr;
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr &= ~(CYGARC_REG_IMM_PISCR_PIE);
piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
{
// Real Time Clock Second
cyg_uint16 rtcsc;
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // Accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -