📄 var_regs.h
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#define CYGARC_REG_IMM_MIOS1LVL_LVL_SHIFT 8
#define CYGARC_REG_IMM_MIOS1LVL_TM 0x00c0
#define CYGARC_REG_IMM_MIOS1LVL_TM_SHIFT 6
//-----------------------------------------------------------------------------
// Periodic interrupt timer count
#define CYGARC_REG_IMM_PITC_COUNT_SHIFT 16 // count is stored in bits 0-15
//-----------------------------------------------------------------------------
// System clock control
#define CYGARC_REG_IMM_SCCR_TBS 0x02000000 // Time base source
#define CYGARC_REG_IMM_SCCR_RTDIV 0x01000000 // rtc clock divide
#define CYGARC_REG_IMM_SCCR_RTSEL 0x00100000 // rtc clock select
//-------------------------------------
// TouCAN (CAN 2.0B Controller)
#define CYGARC_REG_IMM_CANICR_IRL 0x0700
#define CYGARC_REG_IMM_CANICR_IRL_SHIFT 8
#define CYGARC_REG_IMM_CANICR_ILBS 0x00c0
#define CYGARC_REG_IMM_CANICR_ILBS_SHIFT 6
#define CYGARC_REG_IMM_TCNMCR_STOP 0x8000
#define CYGARC_REG_IMM_TCNMCR_FRZ 0x4000
#define CYGARC_REG_IMM_TCNMCR_HALT 0x1000
#define CYGARC_REG_IMM_TCNMCR_NOTRDY 0x0800
#define CYGARC_REG_IMM_TCNMCR_WAKEMSK 0x0400
#define CYGARC_REG_IMM_TCNMCR_SOFTRST 0x0200
#define CYGARC_REG_IMM_TCNMCR_FRZACK 0x0100
#define CYGARC_REG_IMM_TCNMCR_SUPV 0x0080
#define CYGRAC_REG_IMM_TCNMCR_SELFWAKE 0x0040
#define CYGARC_REG_IMM_TCNMCR_APS 0x0020
#define CYGARC_REG_IMM_TCNMCR_STOPACK 0x0010
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_BOFFMSK 0x8000
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_ERRMSK 0x4000
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_RXMOD 0x0c00
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_TXMOD 0x0300
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_RXMOD_SHIFT 10
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_TXMOD_SHIFT 8
#define CYGARC_REG_IMM_ESTAT_BITERR 0xc000
#define CYGARC_REG_IMM_ESTAT_ACKERR 0x2000
#define CYGARC_REG_IMM_ESTAT_CRCERR 0x1000
#define CYGARC_REG_IMM_ESTAT_FORMERR 0x0800
#define CYGARC_REG_IMM_ESTAT_STUFFERR 0x0400
#define CYGARC_REG_IMM_ESTAT_TXWARN 0x0200
#define CYGARC_REG_IMM_ESTAT_RXWARN 0x0100
#define CYGARC_REG_IMM_ESTAT_IDLE 0x0080
#define CYGARC_REG_IMM_ESTAT_TX_RX 0x0040
#define CYGARC_REG_IMM_ESTAT_FCS 0x0030
#define CYGARC_REG_IMM_ESTAT_BOFFINT 0x0004
#define CYGARC_REG_IMM_ESTAT_ERRINT 0x0002
#define CYGARC_REG_IMM_ESTAT_WAKEINT 0x0001
#define CYGARC_REG_IMM_ESTAT_BITERR_SHIFT 14
#define CYGARC_REG_IMM_ESTAT_FCS_SHIFT 4
//-----------------------------------------------------------------------------
// All registers in the internal memory map
#define CYGARC_REG_IMM_BASE (0x002fc000)
// General register definitions
#define CYGARC_REG_IMM_SIUMCR (CYGARC_REG_IMM_BASE+0x0000)
#define CYGARC_REG_IMM_SYPCR (CYGARC_REG_IMM_BASE+0x0004)
#define CYGARC_REG_IMM_SWSR (CYGARC_REG_IMM_BASE+0x000e)
#define CYGARC_REG_IMM_SIPEND (CYGARC_REG_IMM_BASE+0x0010)
#define CYGARC_REG_IMM_SIMASK (CYGARC_REG_IMM_BASE+0x0014)
#define CYGARC_REG_IMM_SIEL (CYGARC_REG_IMM_BASE+0x0018)
#define CYGARC_REG_IMM_SIVEC (CYGARC_REG_IMM_BASE+0x001c)
#define CYGARC_REG_IMM_TESR (CYGARC_REG_IMM_BASE+0x0020)
#define CYGARC_REG_IMM_SGPIODT1 (CYGARC_REG_IMM_BASE+0x0024)
#define CYGARC_REG_IMM_SGPIODT2 (CYGARC_REG_IMM_BASE+0x0028)
#define CYGARC_REG_IMM_SGPIOCR (CYGARC_REG_IMM_BASE+0x002c)
#define CYGARC_REG_IMM_EMCR (CYGARC_REG_IMM_BASE+0x0030)
#define CYGARC_REG_IMM_PDMCR (CYGARC_REG_IMM_BASE+0x003c)
// Memory controller registers
#define CYGARC_REG_IMM_BR0 (CYGARC_REG_IMM_BASE+0x0100)
#define CYGARC_REG_IMM_OR0 (CYGARC_REG_IMM_BASE+0x0104)
#define CYGARC_REG_IMM_BR1 (CYGARC_REG_IMM_BASE+0x0108)
#define CYGARC_REG_IMM_OR1 (CYGARC_REG_IMM_BASE+0x010c)
#define CYGARC_REG_IMM_BR2 (CYGARC_REG_IMM_BASE+0x0110)
#define CYGARC_REG_IMM_OR2 (CYGARC_REG_IMM_BASE+0x0114)
#define CYGARC_REG_IMM_BR3 (CYGARC_REG_IMM_BASE+0x0118)
#define CYGARC_REG_IMM_OR3 (CYGARC_REG_IMM_BASE+0x011c)
#define CYGARC_REG_IMM_DMBR (CYGARC_REG_IMM_BASE+0x0140)
#define CYGARC_REG_IMM_DMOR (CYGARC_REG_IMM_BASE+0x0144)
#define CYGARC_REG_IMM_MSTAT (CYGARC_REG_IMM_BASE+0x0178)
// System integration timers
#define CYGARC_REG_IMM_TBSCR (CYGARC_REG_IMM_BASE+0x0200)
#define CYGARC_REG_IMM_TBREF0 (CYGARC_REG_IMM_BASE+0x0204)
#define CYGARC_REG_IMM_TBREF1 (CYGARC_REG_IMM_BASE+0x0208)
#define CYGARC_REG_IMM_RTCSC (CYGARC_REG_IMM_BASE+0x0220)
#define CYGARC_REG_IMM_RTC (CYGARC_REG_IMM_BASE+0x0224)
#define CYGARC_REG_IMM_RTSEC (CYGARC_REG_IMM_BASE+0x0228)
#define CYGARC_REG_IMM_RTCAL (CYGARC_REG_IMM_BASE+0x022c)
#define CYGARC_REG_IMM_PISCR (CYGARC_REG_IMM_BASE+0x0240)
#define CYGARC_REG_IMM_PITC (CYGARC_REG_IMM_BASE+0x0244)
#define CYGARC_REG_IMM_PITR (CYGARC_REG_IMM_BASE+0x0248)
// Clocks and resets
#define CYGARC_REG_IMM_SCCR (CYGARC_REG_IMM_BASE+0x0280)
#define CYGARC_REG_IMM_PLPRCR (CYGARC_REG_IMM_BASE+0x0284)
#define CYGARC_REG_IMM_RSR (CYGARC_REG_IMM_BASE+0x0288)
#define CYGARC_REG_IMM_COLIR (CYGARC_REG_IMM_BASE+0x028c)
#define CYGARC_REG_IMM_VSRMCR (CYGARC_REG_IMM_BASE+0x0290)
// System IntegrationTimer Keys
#define CYGARC_REG_IMM_TBSCRK (CYGARC_REG_IMM_BASE+0x0300)
#define CYGARC_REG_IMM_TBREF0K (CYGARC_REG_IMM_BASE+0x0304)
#define CYGARC_REG_IMM_TBREF1K (CYGARC_REG_IMM_BASE+0x0308)
#define CYGARC_REG_IMM_TBK (CYGARC_REG_IMM_BASE+0x030c)
#define CYGARC_REG_IMM_RTCSCK (CYGARC_REG_IMM_BASE+0x0320)
#define CYGARC_REG_IMM_RTCK (CYGARC_REG_IMM_BASE+0x0324)
#define CYGARC_REG_IMM_RTSECK (CYGARC_REG_IMM_BASE+0x0328)
#define CYGARC_REG_IMM_RTCALK (CYGARC_REG_IMM_BASE+0x032c)
#define CYGARC_REG_IMM_PISCRK (CYGARC_REG_IMM_BASE+0x0340)
#define CYGARC_REG_IMM_PITCK (CYGARC_REG_IMM_BASE+0x0344)
// Clocks and reset keys
#define CYGARC_REG_IMM_SCCRK (CYGARC_REG_IMM_BASE+0x0380)
#define CYGARC_REG_IMM_PLPRCRK (CYGARC_REG_IMM_BASE+0x0384)
#define CYGARC_REG_IMM_RSRK (CYGARC_REG_IMM_BASE+0x0388)
//-------------------------------------
// CMF (CDR Mone T FLASH EEPROM)
//-------------------------------------
// CMF_A
#define CYGARC_REG_IMM_CMFMCR_A (CYGARC_REG_IMM_BASE+0x0800)
#define CYGARC_REG_IMM_CMFTST_A (CYGARC_REG_IMM_BASE+0x0804)
#define CYGARC_REG_IMM_CMFCTL_A (CYGARC_REG_IMM_BASE+0x0808)
// CMF_B
#define CYGARC_REG_IMM_CMFMCR_B (CYGARC_REG_IMM_BASE+0x0840)
#define CYGARC_REG_IMM_CMFTST_B (CYGARC_REG_IMM_BASE+0x0844)
#define CYGARC_REG_IMM_CMFCTL_B (CYGARC_REG_IMM_BASE+0x0848)
//-------------------------------------
// DPTRAM (Dual-Port TPU RAM)
//-------------------------------------
#define CYGARC_REG_IMM_DPTMCR (CYGARC_REG_IMM_BASE+0x4000)
#define CYGARC_REG_IMM_RAMTST (CYGARC_REG_IMM_BASE+0x4002)
#define CYGARC_REG_IMM_RAMBAR (CYGARC_REG_IMM_BASE+0x4004)
#define CYGARC_REG_IMM_MISRH (CYGARC_REG_IMM_BASE+0x4006)
#define CYGARC_REG_IMM_MISRL (CYGARC_REG_IMM_BASE+0x4008)
#define CYGARC_REG_IMM_MISCNT (CYGARC_REG_IMM_BASE+0x400a)
//-------------------------------------
// TPU3 (Time processing unit)
//-------------------------------------
// TPU-A
#define CYGARC_REG_IMM_TPUMCR_A (CYGARC_REG_IMM_BASE+0x8000)
#define CYGARC_REG_IMM_TCR_A (CYGARC_REG_IMM_BASE+0x8002)
#define CYGARC_REG_IMM_DSCR_A (CYGARC_REG_IMM_BASE+0x8004)
#define CYGARC_REG_IMM_DSSR_A (CYGARC_REG_IMM_BASE+0x8006)
#define CYGARC_REG_IMM_TICR_A (CYGARC_REG_IMM_BASE+0x8008)
#define CYGARC_REG_IMM_CIER_A (CYGARC_REG_IMM_BASE+0x800a)
#define CYGARC_REG_IMM_CFSR0_A (CYGARC_REG_IMM_BASE+0x800c)
#define CYGARC_REG_IMM_CFSR1_A (CYGARC_REG_IMM_BASE+0x800e)
#define CYGARC_REG_IMM_CFSR2_A (CYGARC_REG_IMM_BASE+0x8010)
#define CYGARC_REG_IMM_CFSR3_A (CYGARC_REG_IMM_BASE+0x8012)
#define CYGARC_REG_IMM_HSQR0_A (CYGARC_REG_IMM_BASE+0x8014)
#define CYGARC_REG_IMM_HSQR1_A (CYGARC_REG_IMM_BASE+0x8016)
#define CYGARC_REG_IMM_HSRR0_A (CYGARC_REG_IMM_BASE+0x8018)
#define CYGARC_REG_IMM_HSRR1_A (CYGARC_REG_IMM_BASE+0x801a)
#define CYGARC_REG_IMM_CPR0_A (CYGARC_REG_IMM_BASE+0x801c)
#define CYGARC_REG_IMM_CPR1_A (CYGARC_REG_IMM_BASE+0x801e)
#define CYGARC_REG_IMM_CISR_A (CYGARC_REG_IMM_BASE+0x8020)
#define CYGARC_REG_IMM_LR_A (CYGARC_REG_IMM_BASE+0x8022)
#define CYGARC_REG_IMM_SGLR_A (CYGARC_REG_IMM_BASE+0x8024)
#define CYGARC_REG_IMM_DCNR_A (CYGARC_REG_IMM_BASE+0x8026)
#define CYGARC_REG_IMM_TPUMCR2_A (CYGARC_REG_IMM_BASE+0x8028)
#define CYGARC_REG_IMM_TPUMCR3_A (CYGARC_REG_IMM_BASE+0x802a)
#define CYGARC_REG_IMM_ISDR_A (CYGARC_REG_IMM_BASE+0x802c)
#define CYGARC_REG_IMM_ISCR_A (CYGARC_REG_IMM_BASE+0x802e)
// TPU-B
#define CYGARC_REG_IMM_TPUMCR_B (CYGARC_REG_IMM_BASE+0x8400)
#define CYGARC_REG_IMM_TCR_B (CYGARC_REG_IMM_BASE+0x8402)
#define CYGARC_REG_IMM_DSCR_B (CYGARC_REG_IMM_BASE+0x8404)
#define CYGARC_REG_IMM_DSSR_B (CYGARC_REG_IMM_BASE+0x8406)
#define CYGARC_REG_IMM_TICR_B (CYGARC_REG_IMM_BASE+0x8408)
#define CYGARC_REG_IMM_CIER_B (CYGARC_REG_IMM_BASE+0x840a)
#define CYGARC_REG_IMM_CFSR0_B (CYGARC_REG_IMM_BASE+0x840c)
#define CYGARC_REG_IMM_CFSR1_B (CYGARC_REG_IMM_BASE+0x840e)
#define CYGARC_REG_IMM_CFSR2_B (CYGARC_REG_IMM_BASE+0x8410)
#define CYGARC_REG_IMM_CFSR3_B (CYGARC_REG_IMM_BASE+0x8412)
#define CYGARC_REG_IMM_HSQR0_B (CYGARC_REG_IMM_BASE+0x8414)
#define CYGARC_REG_IMM_HSQR1_B (CYGARC_REG_IMM_BASE+0x8416)
#define CYGARC_REG_IMM_HSRR0_B (CYGARC_REG_IMM_BASE+0x8418)
#define CYGARC_REG_IMM_HSRR1_B (CYGARC_REG_IMM_BASE+0x841a)
#define CYGARC_REG_IMM_CPR0_B (CYGARC_REG_IMM_BASE+0x841c)
#define CYGARC_REG_IMM_CPR1_B (CYGARC_REG_IMM_BASE+0x841e)
#define CYGARC_REG_IMM_CISR_B (CYGARC_REG_IMM_BASE+0x8420)
#define CYGARC_REG_IMM_LR_B (CYGARC_REG_IMM_BASE+0x8422)
#define CYGARC_REG_IMM_SGLR_B (CYGARC_REG_IMM_BASE+0x8424)
#define CYGARC_REG_IMM_DCNR_B (CYGARC_REG_IMM_BASE+0x8426)
#define CYGARC_REG_IMM_TPUMCR2_B (CYGARC_REG_IMM_BASE+0x8428)
#define CYGARC_REG_IMM_TPUMCR3_B (CYGARC_REG_IMM_BASE+0x842a)
#define CYGARC_REG_IMM_ISDR_B (CYGARC_REG_IMM_BASE+0x842c)
#define CYGARC_REG_IMM_ISCR_B (CYGARC_REG_IMM_BASE+0x842e)
//-------------------------------------
// QADC64 (Queued Analog-to-digital Converter)
//-------------------------------------
// QUADC-A
#define CYGARC_REG_IMM_QUADC64MCR_A (CYGARC_REG_IMM_BASE+0x8800)
#define CYGARC_REG_IMM_QUADC64TEST_A (CYGARC_REG_IMM_BASE+0x8802)
#define CYGARC_REG_IMM_QUADC64INT_A (CYGARC_REG_IMM_BASE+0x8804)
#define CYGARC_REG_IMM_PORTQA_A_PORTQB_A (CYGARC_REG_IMM_BASE+0x8806)
#define CYGARC_REG_IMM_DDRQA_A_DDRQB_A (CYGARC_REG_IMM_BASE+0x8808)
#define CYGARC_REG_IMM_QUACR0_A (CYGARC_REG_IMM_BASE+0x880a)
#define CYGARC_REG_IMM_QUACR1_A (CYGARC_REG_IMM_BASE+0x880c)
#define CYGARC_REG_IMM_QUACR2_A (CYGARC_REG_IMM_BASE+0x880e)
#define CYGARC_REG_IMM_QUASR0_A (CYGARC_REG_IMM_BASE+0x8810)
#define CYGARC_REG_IMM_QUASR1_A (CYGARC_REG_IMM_BASE+0x8812)
#define CYGARC_REG_IMM_CCW_A (CYGARC_REG_IMM_BASE+0x8a00)
#define CYGARC_REG_IMM_RJURR_A (CYGARC_REG_IMM_BASE+0x8a80)
#define CYGARC_REG_IMM_LJSRR_A (CYGARC_REG_IMM_BASE+0x8b00)
#define CYGARC_REG_IMM_LJURR_A (CYGARC_REG_IMM_BASE+0x8b80)
// QUADC-B
#define CYGARC_REG_IMM_QUADC64MCR_B (CYGARC_REG_IMM_BASE+0x8c00)
#define CYGARC_REG_IMM_QUADC64TEST_B (CYGARC_REG_IMM_BASE+0x8c02)
#define CYGARC_REG_IMM_QUADC64INT_B (CYGARC_REG_IMM_BASE+0x8c04)
#define CYGARC_REG_IMM_PORTQA_B_PORTQB_B (CYGARC_REG_IMM_BASE+0x8c06)
#define CYGARC_REG_IMM_DDRQA_B_DDRQB_B (CYGARC_REG_IMM_BASE+0x8c08)
#define CYGARC_REG_IMM_QUACR0_B (CYGARC_REG_IMM_BASE+0x8c0a)
#define CYGARC_REG_IMM_QUACR1_B (CYGARC_REG_IMM_BASE+0x8c0c)
#define CYGARC_REG_IMM_QUACR2_B (CYGARC_REG_IMM_BASE+0x8c0e)
#define CYGARC_REG_IMM_QUASR0_B (CYGARC_REG_IMM_BASE+0x8c10)
#define CYGARC_REG_IMM_QUASR1_B (CYGARC_REG_IMM_BASE+0x8c12)
#define CYGARC_REG_IMM_CCW_B (CYGARC_REG_IMM_BASE+0x8e00)
#define CYGARC_REG_IMM_RJURR_B (CYGARC_REG_IMM_BASE+0x8e80)
#define CYGARC_REG_IMM_LJSRR_B (CYGARC_REG_IMM_BASE+0x8f00)
#define CYGARC_REG_IMM_LJURR_B (CYGARC_REG_IMM_BASE+0x8f80)
//-------------------------------------
// QSMCM (Queued Serial Multi-Channel Module)
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