var_regs.h

开放源码实时操作系统源码.

#ifndef CYGONCE_HAL_VAR_REGS_H
#define CYGONCE_HAL_VAR_REGS_H

//==========================================================================
//
//      var_regs.h
//
//      PowerPC 5xx variant CPU definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Bob Koninckx
// Contributors: Bob Koninckx
// Date:         2001-09-12
// Purpose:      Provide MPC5xx register definitions
// Description:  Provide MPC5xx register definitions
//               The short difinitions (sans CYGARC_REG_) are exported only
//               if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
// Usage:        Included via the acrhitecture register header:
//               #include <cyg/hal/ppc_regs.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

//--------------------------------------------------------------------------
// Special purpose registers
// 
#define CYGARC_REG_XER          1
#define CYGARC_REG_LR           8
#define CYGARC_REG_CTR          9
#define CYGARC_REG_EIE          80
#define CYGARC_REG_EID          81
#define CYGARC_REG_NRI          82
#define CYGARC_REG_CMPA         144
#define CYGARC_REG_CMPB         145
#define CYGARC_REG_CMPC         146
#define CYGARC_REG_CMPD         147
#define CYGARC_REG_ECR          148
#define CYGARC_REG_DER          149
#define CYGARC_REG_COUNTA       150
#define CYGARC_REG_COUNTB       151
#define CYGARC_REG_CMPE         152
#define CYGARC_REG_CMPF         153
#define CYGARC_REG_CMPG         154
#define CYGARC_REG_CMPH         155
#define CYGARC_REG_LCTRL1       156
#define CYGARC_REG_LCTRL2       157
#define CYGARC_REG_BAR          159
#define CYGARC_REG_MI_GRA       528
#define CYGARC_REG_L2U_GRA      536
#define CYGARC_REG_BBCMCR       560
#define CYGARC_REG_L2U_MCR      568
#define CYGARC_REG_DPDR         630
#define CYGARC_REG_IMMR         638
#define CYGARC_REG_MI_RBA0      784
#define CYGARC_REG_MI_RBA1      785
#define CYGARC_REG_MI_RBA2      786
#define CYGARC_REG_MI_RBA3      787
#define CYGARC_REG_L2U_RBA0     792
#define CYGARC_REG_L2U_RBA1     793
#define CYGARC_REG_L2U_RBA2     794
#define CYGARC_REG_L2U_RBA3     795
#define CYGARC_REG_MI_RA0       816
#define CYGARC_REG_MI_RA1       817
#define CYGARC_REG_MI_RA2       818
#define CYGARC_REG_MI_RA3       819
#define CYGARC_REG_L2U_RA0      824
#define CYGARC_REG_L2U_RA1      825
#define CYGARC_REG_L2U_RA2      826
#define CYGARC_REG_L2U_RA3      827
#define CYGARC_REG_FPECR        1022

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
//# define XER                CYGARC_REG_XER // Leave these out, they conflict with GDB stubs
//# define LR                 CYGARC_REG_LR  // are not used anyway
# define CTR                CYGARC_REG_CTR
# define EIE                CYGARC_REG_EIE
# define EID                CYGARC_REG_EID  
# define NRI                CYGARC_REG_NRI
# define CMPA               CYGARC_REG_CMPA
# define CMPB               CYGARC_REG_CMPB
# define CMPC               CYGARC_REG_CMPC
# define CMPD               CYGARC_REG_CMPD
# define ECR                CYGARC_REG_ECR
# define DER                CYGARC_REG_DER
# define COUNTA             CYGARC_REG_COUNTA
# define COUNTB             CYGARC_REG_COUNTB
# define CMPE               CYGARC_REG_CMPE
# define CMPF               CYGARC_REG_CMPF
# define CMPG               CYGARC_REG_CMPG
# define CMPH               CYGARC_REG_CMPH
# define LCTRL1             CYGARC_REG_LCTRL1
# define LCTRL2             CYGARC_REG_LCTRL2
# define BAR                CYGARC_REG_BAR
# define MI_GRA             CYGARC_REG_MI_GRA
# define L2U_GRA            CYGARC_REG_L2U_GRA
# define BBCMCR             CYGARC_REG_BBCMCR
# define L2U_MCR            CYGARC_REG_L2U_MCR
# define DPDR               CYGARC_REG_DPDR
# define IMMR               CYGARC_REG_IMMR
# define MI_RBA0            CYGARC_REG_MI_RBA0
# define MI_RBA1            CYGARC_REG_MI_RBA1
# define MI_RBA2            CYGARC_REG_MI_RBA2
# define MI_RBA3            CYGARC_REG_MI_RBA3
# define L2U_RBA0           CYGARC_REG_L2U_RBA0
# define L2U_RBA1           CYGARC_REG_L2U_RBA1
# define L2U_RBA2           CYGARC_REG_L2U_RBA2
# define L2U_RBA3           CYGARC_REG_L2U_RBA3
# define MI_RA0             CYGARC_REG_MI_RA0
# define MI_RA1             CYGARC_REG_MI_RA1
# define MI_RA2             CYGARC_REG_MI_RA2
# define MI_RA3             CYGARC_REG_MI_RA3
# define L2U_RA0            CYGARC_REG_L2U_RA0
# define L2U_RA1            CYGARC_REG_L2U_RA1
# define L2U_RA2            CYGARC_REG_L2U_RA2
# define L2U_RA3            CYGARC_REG_L2U_RA3
# define FPECR              CYGARC_REG_FPECR
#endif //#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//-----------------------------------------------------------------------------
// Development Support.
#define CYGARC_REG_DER             149

#define CYGARC_REG_ICTRL           158  // instruction support control reg
#define CYGARC_REG_ICTRL_SERSHOW   0x00000000 // serialized, show cycles
#define CYGARC_REG_ICTRL_NOSERSHOW 0x00000007 //non-serialized&no show cycles

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define DER             CYGARC_REG_DER

#define ICTRL           CYGARC_REG_ICTRL
#define ICTRL_SERSHOW   CYGARC_REG_ICTRL_SERSHOW
#define ICTRL_NOSERSHOW CYGARC_REG_ICTRL_NOSERSHOW
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//-----------------------------------------------------------------------------
// Bit definitions
//-----------------------------------------------------------------------------
// The internal memory map register (IMMR)
#define CYGARC_REG_IMM_IMMR_PARTNUM    0xff000000  // part number mask (ro)
#define CYGARC_REG_IMM_IMMR_MASKNUM    0x00ff0000  // mask number mask (ro)
#define CYGARC_REG_IMM_IMMR_ISB        0x0000000e  // internal space base
#define CYGARC_REG_IMM_IMMR_CLES       0x00000100  // core little endian swap
#define CYGARC_REG_IMM_IMMR_FLEN       0x00000800  // flash enable

//-----------------------------------------------------------------------------
// System protection control (SYPCR)
#define CYGARC_REG_IMM_SYPR_SWTC_MASK  0xffff0000
#define CYGARC_REG_IMM_SYPR_BMT_MASK   0x0000ff00
#define CYGARC_REG_IMM_SYPR_BME        0x00000080
#define CYGARC_REG_IMM_SYPR_SWF        0x00000008
#define CYGARC_REG_IMM_SYPR_SWE        0x00000004
#define CYGARC_REG_IMM_SYPR_SWRI       0x00000002 
#define CYGARC_REG_IMM_SYPR_SWP        0x00000001

//-----------------------------------------------------------------------------
// Interrupt pend register (SIPEND)
#define CYGARC_REG_IMM_SIPEND_IRQ0     0x80000000  // External interrupt priority 0
#define CYGARC_REG_IMM_SIPEND_LVL0     0x40000000  // Internal interrupt level 0
#define CYGARC_REG_IMM_SIPEND_IRQ1     0x20000000  // External interrupt priority 1
#define CYGARC_REG_IMM_SIPEND_LVL1     0x10000000  // Internal interrupt level 1
#define CYGARC_REG_IMM_SIPEND_IRQ2     0x08000000  // External interrupt priority 2
#define CYGARC_REG_IMM_SIPEND_LVL2     0x04000000  // Internal interrupt level 2
#define CYGARC_REG_IMM_SIPEND_IRQ3     0x02000000  // External interrupt priority 3
#define CYGARC_REG_IMM_SIPEND_LVL3     0x01000000  // Internal interrupt level 3
#define CYGARC_REG_IMM_SIPEND_IRQ4     0x00800000  // External interrupt prioeity 4
#define CYGARC_REG_IMM_SIPEND_LVL4     0x00400000  // Internal interrupt level 4
#define CYGARC_REG_IMM_SIPEND_IRQ5     0x00200000  // External interrupt priority 5
#define CYGARC_REG_IMM_SIPEND_LVL5     0x00100000  // Internal interrupt level 5
#define CYGARC_REG_IMM_SIPEND_IRQ6     0x00080000  // External interrupt priority 6
#define CYGARC_REG_IMM_SIPEND_LVL6     0x00040000  // Internal interrupt level 6
#define CYGARC_REG_IMM_SIPEND_IRQ7     0x00020000  // External interrupt priority 7
#define CYGARC_REG_IMM_SIPEND_LVL7     0x00010000  // Internal interrupt level 7

//-----------------------------------------------------------------------------
// Interrupt mask register (SIMASK)
#define CYGARC_REG_IMM_SIMASK_IRM0     0x80000000  // External interrupt priority 0
#define CYGARC_REG_IMM_SIMASK_LVM0     0x40000000  // Internal interrupt level 0
#define CYGARC_REG_IMM_SIMASK_IRM1     0x20000000  // External interrupt priority 1
#define CYGARC_REG_IMM_SIMASK_LVM1     0x10000000  // Internal interrupt level 1
#define CYGARC_REG_IMM_SIMASK_IRM2     0x08000000  // External interrupt priority 2
#define CYGARC_REG_IMM_SIMASK_LVM2     0x04000000  // Internal interrupt level 2
#define CYGARC_REG_IMM_SIMASK_IRM3     0x02000000  // External interrupt priority 3
#define CYGARC_REG_IMM_SIMASK_LVM3     0x01000000  // Internal interrupt level 3
#define CYGARC_REG_IMM_SIMASK_IRM4     0x00800000  // External interrupt priority 4
#define CYGARC_REG_IMM_SIMASK_LVM4     0x00400000  // Internal interrupt level 4
#define CYGARC_REG_IMM_SIMASK_IRM5     0x00200000  // External interrupt priority 5
#define CYGARC_REG_IMM_SIMASK_LVM5     0x00100000  // Internal interrupt level 5
#define CYGARC_REG_IMM_SIMASK_IRM6     0x00080000  // External interrupt priority 6
#define CYGARC_REG_IMM_SIMASK_LVM6     0x00040000  // Internal interrupt level 6
#define CYGARC_REG_IMM_SIMASK_IRM7     0x00020000  // External interrupt priority 7
#define CYGARC_REG_IMM_SIMASK_LVM7     0x00010000  // Internal interrupt level 7

//-----------------------------------------------------------------------------
// Interrupt edge level register (CIEL)
#define CYGARC_REG_IMM_SIEL_ED0        0x80000000  // Falling edge external interrupt priority 0
#define CYGARC_REG_IMM_SIEL_WM0        0x40000000  // Wake-up mask external interrupt priority 0
#define CYGARC_REG_IMM_SIEL_ED1        0x20000000  // Falling edge external interrupt priority 1
#define CYGARC_REG_IMM_SIEL_WM1        0x10000000  // Wake-up mask external interrupt priority 1
#define CYGARC_REG_IMM_SIEL_ED2        0x08000000  // Falling edge external interrupt priority 2
#define CYGARC_REG_IMM_SIEL_WM2        0x04000000  // Wake-up mask external interrupt priority 2
#define CYGARC_REG_IMM_SIEL_ED3        0x02000000  // Falling edge external interrupt priority 3
#define CYGARC_REG_IMM_SIEL_WM3        0x01000000  // Wake-up mask external interrupt priority 3