📄 ts6.s
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addi r3,0,0x00FF # Load 0x000000FF into r3
stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31]
#-------------------------------------------------------------------------
# Program the PSDMR keeping refresh services off and changing the
# SDRAM operation to "CBR Refresh". This step is responsible for issuing
# a minimum of 8 auto-refresh commands. This is done by the SDRAM machine
# by issuing the CBR Refresh command by programming the OP field of the
# PSDMR register and writing 0xFF 8 times to an arbitrary address.
#-------------------------------------------------------------------------
# Clear refresh enable bit (bit 1 = 0)
# Set OP mode to CBR Refresh (bits 2-4 = 001b)
addis r3,0,0x8B2E
ori r3,r3,0xB452
stw r3,CYGARC_REG_IMM_PSDMR(r4)
#------------------------------------------
# Loop 8 times, writing 0xFF to address 0
#------------------------------------------
addi r6,0,0x0008
mtspr CYGARC_REG_CTR,r6 # Load CTR with 8. The CTR special purpose
# is spr 9
addi r3,0,0x00FF # Load 0x000000FF into r3
write_loop:
stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31]
bc 16,0,write_loop # Decrement CTR, then branch if the decremented CTR
# is not equal to 0
#-------------------------------------------------------------------------
# Program the PSDMR again turning off refresh services and changing the
# SDRAM operation to "Mode Register Write". Then do a single write to an
# arbitrary location. The various fields that will be programmed in the
# mode register on the SDRAM were specified in fields of the PSDMR, like
# the BR (burst length) and the CL (CAS Latency) field.
#-------------------------------------------------------------------------
# Clear refresh enable bit (bit 1 = 0)
# Set OP mode to Mode Register Write (bits 2-4 = 011b)
addis r3,0,0x9B2E
ori r3,r3,0xB452
stw r3,CYGARC_REG_IMM_PSDMR(r4)
addi r3,0,0x00FF # Load 0x000000FF into r3
stb r3,0(r0) # Write 0xFF to address 0 - bits [24-31]
#-------------------------------------------------------------------------
# Program the PSDMR one last time turning on refresh services and changing
# the SDRAM operation to "Normal Operation".
#-------------------------------------------------------------------------
# Set refresh enable bit (bit 1 = 1)
# Set OP mode to Normal Operation (bits 2-4 = 000b)
addis r3,0,0xC32E
ori r3,r3,0xB452
stw r3,CYGARC_REG_IMM_PSDMR(r4)
#----------------------------
# return from init_60x_sdram
#----------------------------
bclr 20,0 # jump unconditionally to effective address in Link
# register
init_user_leds:
# Initialize Port A pins
# Pin 30-31 GPIO wires to RF board
# Pin 29 TS_RESET_L, output, Tiger Sharc Reset line, drive low on
# initialization.
# Pin 28 LB_ENB_L, output, Link Port Buffer enable, drive high on
# initialization.
# Pin 26-27 GPIO wires to RF board
# Pin 18-23 GPIO wires, one each to Tiger Sharc
# Pin 12-17 Interrupt wires to Sharc, output, drive high on
# initialization.
# Set Port A pins 12-31 for general purpose, i.e., to 0
# Set Port A pins 12-17, 28, 29 (add more later) for output (set to 1)
# for lines that we do not know, set to 0 (input)
# Set Port A output pins High or Low, as specified
#define TS6_PPARA_INIT_MASK 0xFFF00000
#define TS6_PDIRA_INIT_MASK 0x3003F000
#define TS6_PDATA_INIT_MASK 0x1003F000
# Initialize Port B Pins 4,5,6,7 general purpose IO
# Pin 4 LED 18, Red
# Pin 5 LED 18, Green
# Pin 6 LED 17, Red
# Pin 7 LED 17, Green
mfspr r30,CYGARC_REG_LR # Save the Link Register value. The link registers
# value will be restored so that this function
# can return to the calling address.
addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We
# add 0x10000 because using relative addressing
# in load and store instructions only allow a
# offset from the base of +/-32767.
addi r6,0,0 # R6 = 0
lwz r3,0x0D24(r4) # R3 = PPARB
rlwimi r3,r6,0,4,7
# and r3,r3,r6 # Clear bits 4,5,6,7
stw r3,0x0D24(r4) # Store 0 to PPARB to set 4 bits to general
# purpose.
addis r6,0,0x0F00 # R6 = 0x0F000000
lwz r3,0x0D20(r4) # R3 = PDIRB
or r3,r3,r6 # Set bits 4,5,6,7
stw r3,0x0D20(r4) # Store r3 to PDIRB to set 4 bits as outputs.
#-----------------------
# return from init_user_leds
#-----------------------
mtspr CYGARC_REG_LR,r30 # restore original Link Register value
bclr 20,0 # jump unconditionally to effective address in Link
# register
flash_leds_forever:
# This function assumes that the Port B registers have been properly
# initialized so the LEDs will function. See init_user_leds.
addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We
# add 0x10000 because using relative addressing
# in load and store instructions only allow a
# offset from the base of +/-32767.
addi r3,0,0x000F # R3 will hold value of LEDs, start with all off
flash_again:
#~~~~~~~~~~~~~~~~~~~~~~~~~~
# Load count of 0x0040000
#~~~~~~~~~~~~~~~~~~~~~~~~~~
addis r5,r0,4
#~~~~~~~~~~~~~~~~~
# Delay Loop here
#~~~~~~~~~~~~~~~~~
check_count:
#-------------------------
# while (count != 0)
#-------------------------
cmpi 0,0,r5,0
bc 12,2,count_done # if zero branch to count_done
#-----------
# count--;
#-----------
addi r5,r5,-1
b check_count
count_done:
#increment r3
addi r3,r3,1
rlwinm r6,r3,24,4,7 # left shift r3 by 24, mask r3 so
# so bits 4 -7 are all thats left,
# and store result in r6
stw r6,0x0D30(r4) # Store new value to PDATB Register
b flash_again
#ifdef CYG_HAL_STARTUP_ROM
# This routine will test the memory from address 0x0
# thru 0x03ffffff (64MByte) by writing the address to the address
# for all addresses, and then reading each of those values.
#
# Use two loops, the outer loop goes from 0 to 0x3ff and counts
# by 1. The inner loop goes from 0 to 0xfffc and counts by 4.
.globl memory_test
memory_test:
#Turn on Green Led
# For TS6 board, LD17 will signal running status
# LD17 == GREEN ==> writing data to memory
# LD17 == RED ==> reading data from memory and comparing
# LD17 == OFF ==> test completed
# For TS6 board, LD18 will test status
# LD18 == GREEN ==> all memory location contained expected values
# LD18 == RED ==> error reading memory location,
# r6 contains address and expected value
# r10 contains actual value read
# LD18 == OFF ==> test not completed
#
# r23 will hold the largest memory value to test
# r29 will hold the smallest memory value (0x0 <= r29 < 0x10000)
# NOTE read the code to find out exactly how the test is run.
bl init_user_leds
addis r23, 0, 0x0400 # Initialize r23 to 64 MBytes
addis r29, 0, 0x0 # Initialize r29 to 0
addis r4,0,0x0471 # IMMR base addr = 0x04700000+10000. We
# add 0x10000 because using relative addressing
# in load and store instructions only allow a
# offset from the base of +/-32767.
# LD18 off, LED17 Green
lwz r3,0x0D30(r4) # r3 = PDATB value
addis r5,0,0x0d00 # LD18 off, LED17 Green
rlwimi r3,r5,0,4,7
stw r3,0x0D30(r4)
#addis r3,0,0x0200 # r3 will hold the outer counter, start at 0x3ff0000
#addis r9,0,0x0000 # r9 will hold the stop address
mr r3, r23 # r23 holds the start value, set with debugger
mr r9, r29 # r29 holds the stop value, set with debugger
memwrite_loop1:
addis r3,r3,-1 # subtract 0x10000 from r3
addis r5,0,0x1 # r5 will hold inner counter, start at 0xfffc
# generate the value to store in the address. It is the value in r3
# shifted by 16 plus the vale in r5.
memwrite_loop2:
addi r5,r5,-4 # subtract 1 from r5
add r6,r3,r5
stwx r6,r5,r3 # Store the value at r6 in the memory addressed
# by the sum of r3 and r5
nop
nop
nop
# lwzx r10,r5,r3 # Read the value into r10 from the memory addressed
# by the sum of r3 and r5
# cmpw r6,r10 # compare values to confirm write
# bne mem_error
cmpi 0,0,r5,0
bne memwrite_loop2 # branch if r5 != 0
# Check if r3 is 0
cmp 0,0,r3,r9
bne memwrite_loop1 # branch if r3 != 0
# Writing to memory complete, start reading and validating
# LD18 off, LED17 Red
lwz r3,0x0D30(r4) # r3 = PDATB value
addis r5,0,0x0e00 # LD18 off, LED17 Red
rlwimi r3,r5,0,4,7
stw r3,0x0D30(r4)
#addis r3,0,0x0200 # r3 will hold the outer counter, start at 0x3ff0000
#addis r9,0,0x0000 # r9 will hold the stop address
mr r3, r23 # r23 holds the start value, set with debugger
mr r9, r29 # r29 holds the stop value, set with debugger
memread_loop1:
addis r3,r3,-1 # subtract 0x10000 from r3
addis r5,0,0x1 # r5 will hold inner counter, start at 0xfffc
# generate the value to store in the address. It is the value in r3
# shifted by 16 plus the vale in r5.
memread_loop2:
addi r5,r5,-4 # subtract 1 from r5
add r16,r3,r5
lwzx r20,r5,r3 # Read the value into r20 from the memory addressed
# by the sum of r3 and r5
cmpw r16,r20 # compare values
bne mem_error
cmpi 0,0,r5,0
bne memread_loop2 # branch if r5 != 0
# Check if r3 is 0
cmp 0,0,r3,r9
bne memread_loop1 # branch if r3 != 0
# We get here if memory test passes
# LD18 Green, LED17 Off
lwz r3,0x0D30(r4) # r3 = PDATB value
addis r5,0,0x0700 # LD18 Green, LED17 Off
rlwimi r3,r5,0,4,7
stw r3,0x0D30(r4)
addis r7,0,0x0E00
stw r7,0(r8)
b branch_to_dot
mem_error:
# We get here if a memory error was detected
# LD18 Red, LED17 Off
lwz r3,0x0D30(r4) # r3 = PDATB value
addis r5,0,0x0b00 # LD18 off, LED17 Red
rlwimi r3,r5,0,4,7
stw r3,0x0D30(r4)
#endif
branch_to_dot:
b branch_to_dot
#------------------------------------------------------------------------------
# end of ts6.S
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