📄 ts6.s
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# Feb /27/02 pfine Modified the Motorola code to work for the TS6
# board.
# Jan /9/99 jay Initial Release
#
#########################################################################
init_60x_sdram:
# The Delphi MPC8260 TigerSHARC-6 Board is stocked with a 64 MByte
# SDRAM DIMM module (WINTEC W9Q308647PA-222H). The DIMM module consists
# of 4 Micron Technology 128 Mbit SDRAM modules, each having 12 row
# by 9 columns by 4 banks. The part number for the Micron SDRAM
# is 48LC8M16A2. The Refresh Period is 64 milliseconds for all 4096
# rows, or 15.625 usec per row.
#
# NOTE - The spec sheet for the WINTEC DIMM claims that the device
# has 12/11/2 rows/columns/banks, but the spec sheet for the Micron
# SDRAM chips says 12/9/4. The 4 Banks seems to work.
# The TS6 board has the 60x Bus SDRAM connected to CS5, so use BR5, OR5.
#-------------------------------------------------------------------------
# Program the 60x Bus Assigned SDRAM Refresh Timer (PSRT).
# See SIU initialization programming for details of why 16 is the
# value for the PSRT.
#-------------------------------------------------------------------------
addi r5,0,0x0010 # load 0x10 or 16
stb r5,CYGARC_REG_IMM_PSRT(r4) # store byte - bits[24-31]
#########################
# Program Bank Registers
#########################
#-------------------------------------------------------------------------
# Base Register 5 (BR5): Bank 5 is assigned to the 64 Mbyte 60x SDRAM DIMM
# that resides on the MPC8260 TS6 board. The
# particulars are defined here.
#
# - BA (Base Address) = 0x0000+0b for a total of 17 address bits. This
# value represents the upper 17 bits of the base
# address.
#
# - Bits 17-18 reserved. = 00 = cleared to 0.
#
# - PS (Port Size) = 00b = 64 bit port size
#
# - DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# - WP (Write Protect) = 0 = both read and write accesses are allowed
#
# - MS (Machine Select) = 010 = SDRAM Machine for 60x bus Selected
#
# - EMEMC (External Memory Controller Enable) = 0 =
#
# Accesses are handled by the memory controller according to MSEL.
#
# - ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# - DR (Delayed Read) = 0 = Normal operation.
#
# - V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
addis r3,0,0x0000 # R3 holds the value temporarily
ori r3,r3,0x0041
#-------------------------------------------------------------------------
# Option Register 5 (OR5) for SDRAM Machine use: further SDRAM definitions
#
# - SDAM (SDRAM Address Mask) = 1111 1100 0000b = 0xFC0
# As per the errata to the MPC8260 Users Manual, the SDAM value
# is a 12 bit field (0-11). The 64 MByte block is specified.
#
# - LSDAM (Lower SDRAM Address Mask) = 00000b = Minimum of 1 Mbyte size.
#
# - BPD (Banks Per Device) = 01b = 4 internal banks per device.
#
#
#
# -- The SDRAM is set up to operate in Page Based Interleaving Mode.
#
# - ROWST (Row Start Address Bit) = 0110b = A6 being the row start address
# bit. See the PSDMR programming
# explanation below for details
# of how A6 was determined to be
# the starting row.
# As per the errata to the MPC8260 Users Manual, the ROWST field
# bits 19-22.
#
# - NUMR (Number of Row Address Lines) = 011b = 12 row address lines.
#
# - PMSEL (Page Mode Select) = 1
#
# - IBID (Internal bank interleaving within same device disable) = 1
#
# As per MPC8260 Users Manual, if the SDRAM device is not connected
# to the BNKSEL pins, then this bit should be set. The BNKSEL pins
# are not connected on the TS6 platform.
#
# - Bits 28-31 Reserved - set to 0.
#-------------------------------------------------------------------------
addis r5,0,0xFC00 # R5 holds the value temporarily
ori r5,r5,0x2CF0
#------------------
# Write the values
#------------------
stw r5,CYGARC_REG_IMM_OR5(r4)
stw r3,CYGARC_REG_IMM_BR5(r4)
###########################################
# Perform Initialization sequence to SDRAM
###########################################
#-------------------------------------------------------------------------
# Program the PowerPC SDRAM Mode Registr (PSDMR). This register is used
# to configure operations pertaining to SDRAM. Program the PSDMR, turning
# off refresh services and changing the SDRAM operation to "Precharge all
# banks". Then do a single write to an arbitrary location. Writing 0xFF
# to address 0 will do the trick.
#
# - PBI (Page Based Interleaving) = 1
#
# - RFEN (Refresh Enable) = 0 = Refresh services not required. This bit
# will be set later in this function as a
# last step.
#
# - OP (SDRAM Operation) = xxx Precharge all banks 101b
# CBR Refresh 001b
# Mode register write 011b
# Normal operation 000b
#
# - SDAM (Address Multiplex Size = 011 =
#
# FIXME - This explanation needs to updated.
# The 64 MByte SDRAM DIMM used on the TS6 platform has only 12 address
# pins and 2 bank select pins. The MPC8260 SDRAM memory controller
# must multiplex the 23 MPC8260 address bits (64 MBytes = 2^26, but
# the 3 lsbs are ignored due to the 64 bit depth of the SDRAM) onto
# the available SDRAM pins.
# The following explanation will explain (hopefully) how the 23 bits
# of the effective address (as seen from the MPC8260) will be remapped
# onto the physical pins of the SDRAM device. It is expected that
# the MPC8260 Users Manual (Chapter 10) is necessary to understand
# this explanation.
#
# Page Based Interleaving is chosen as the address multiplexing method.
# The SDRAM device architecture is 12 rows, 9 columns, 4 banks.
#
# The effective address space as seen from the MPC8260 is partitioned
# as follows to map to the architecture of the SDRAM device.
#
# addresses ignored by SDRAM : A29 A30 A31
#
# column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28
#
# bank select addresses: A18 A19
#
# row addresses: A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
#
# These address bits correspond to the effective address which the MPC8260
# is attempting to access. The MPC8260 memory controller, through
# the settings of the BR5/OR5 and PSDMR registers, will remap these
# effective addresses bits onto the physical address pins of the SDRAM
# DIMM.
#
# -1) The SDRAM has a data width of 64 bits, which means that each
# read or write consists of 8 8-bit bytes aligned on an 8 byte
# boundary. Therefore, the lowest three address bits (A29 A30 A31)
# are always ignored, and not physically connected to the SDRAM.
#
# -2) The 9 column address bits select one column of 512 for
# SDRAM read or write. These bits are mapped directly to the
# physical pins on the SDRAM DIMM.
#
# -3) In Page Based Interleaving mode (PSDMR[PBI] = 1) the bank select
# lines are assigned the address lines between the column addresses
# and the row addresses. By setting OR5[BPD] = 01, the memory
# controller knows that there are 4 banks, and therefore 2 bank
# select lines (A18 A19). The TS6 platform has MPC8260 address
# lines A14 and A15 connected to the two bank select pins on the
# DIMM, and therefore PSDMR[BSMA] = 001.
#
# PSDMR[PBI] = 1
# OR5[BPD] = 01
#
# To clarify, selecting PSDMR[BSMA] = 001 tells the memory
# controller to put out the bits corresponding to the bank select
# address bits on the address lines named A14 and A15.
# Those bank select lines correspond to effective address bits
# A18 and A19. So the effective address bits A18 and A19 actually
# are put out onto the A14 and A15 address lines, which are, in
# turn, connected to BA1 and BA0 on the SDRAM DIMM.
#
# PSDMR[BSMA] = 001
#
# -4) The remaining 12 address bits are the row addresses. Simple
# subtraction says that the starting row address bit
# (OR5[ROWST]) is A6 (3 bits not connected, 9 column bits, 2
# bank select bits, 12 row bits).
#
# OR5[NUMR] = 011b ==> 12 rows
# OR5[ROWST] = 0110b ==> A6 is row start address bit
#
# -5) The memory controller must be told how to multiplex the row
# address bits onto the physical pins of the SDRAM device. This
# is accomplished through the PSDMR[SDAM] field.
# Lining up the column and row addresses so that the
# lsb of the row addresses lines up with the lsb of the column
# addresses gives the following arrangemnt:
#
# column addresses: A20 A21 A22 A23 A24 A25 A26 A27 A28
# row addresses: A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
#
# The MPC8260 Users Manual, Table 10-20 shows that PSDMR[SDAM] = 011b
# provides the proper alignment for this multiplexing scheme.
#
# PSDMR[SDAM] = 011b
#
# -6) The final complication in the SDRAM configuration is the SDA10
# control. SDRAM is accessed in a two stage process. In the
# first stage, the row address and bank selects are loaded to the
# SDRAM device. In the second stage, the column address is loaded.
# SDRAM devices multiplex the A10/AP pin for two purposes. In the
# first stage, A10/AP is an address pin. In the second stage, the
# pin is used to determine how precharging is done (this
# explanation will not go into this aspect). Because the A10/AP
# pin is special, the pin is connected physically to a special
# pin on the MPC8260, the PSDA10 pin. The memory controller must
# be told how which address bit is being multiplexed on PSDA10.
#
# The row address bit which is multplexed onto the pin between
# A9 and A11 physical pins on the SDRAM device is this special bit.
# Lining up the physical pins and the MPC8260 address lines (from
# sheet 15 of the TS6 platform schematics) and the line of Table 20
# corresponding to SDAM = 011b
#
# SDRAM physical pins: A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
# MPC8260 address lines:A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28
# row address: A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
#
# It is seen that the row address bit which will appear on the A10
# physical pin is A7 and therefore
#
# PSDMR[SDA10] = 011b ==> Address bit A7 (for PBI = 1)
#
# - BSMA (Bank Select Multiplexed Address line) = 001 = A13-A15
#
# - SDA10 ("A10 Control") = 011 =
#
# FIXME - The following timing values are not optimized. They are the
# same values as were used in the MPC8260 TS6 board, with
# the 16 MByte DIMM and a 66 MHz Bus Frequency.
#
# - RFRC (ReFresh ReCovery) = 101 =
#
# Once a refresh request is granted, the memory controller begins
# issuing auto-refresh commands to each device associated with the
# refresh timer in one clock intervals. After the last REFRESH
# command is issued, the memory controller waits for 7 clocks before
# the ACTIVATE command and before normal read/write operations can
# resume.
#
# - PRETOACT (PREcharge TO ACTivate interval) = 011 =
#
# Wait 3 clock cycles before an activate command. This parameter is
# determined by the requirements of the SDRAM at a particular clock
# speed.
#
# - ACTTORW (ACTivate TO Read/Write interval) = 010 = 2 clock cycles.
#
# - BL (Burst Length) = 0 = SDRAM burst length is 4. This is programmed
# into the SDRAM via the MRS commmand.
#
# - LDOTOPRE (Last Data Out TO PREcharge) = 01 =
#
# The delay required from the last data out to precharge state is 1 clock
# cycle. This parameter is determined by the requirements of the SDRAM at
# a particular clock speed.
#
# - WRC (Write Recovery Time) = 01 =
#
# Time needed to elapse before another operation is 1 clock cycle. This
# parameter is determined by the requirements of the SDRAM at a
# particular clock speed.
#
# - EAMUX (External Address MUltipleXing) = 0 No external address
# multiplexing.
#
# - BUFCMD (Buffer Control Lines) = 0 = Normal timing for the control
# lines.
#
# - CL (CAS Latency) = 10 =
#
# CAS latency is 2. Two cycles after column address is registered, data
# is valid. This parameter is determined by the requirements of the
# SDRAM at a particular clock speed.
#
#-------------------------------------------------------------------------
##################
# Precharge all banks
##################
# Clear refresh enable bit (bit 1 = 0)
# Set OP mode to Precharge (bits 2-4 = 101b)
addis r3,0,0x8B2E
ori r3,r3,0xB452
stw r3,CYGARC_REG_IMM_PSDMR(r4)
addis r0,0,0
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