📄 ts6.s
字号:
# Write the values
#------------------
stw r3,CYGARC_REG_IMM_BR0(r4)
stw r5,CYGARC_REG_IMM_OR0(r4)
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_bcsr
#
# Description: This function programs Base Register 1 and Option Register 1
# designating bank 1 for BCSR0, BCSR1, and BCSR2 on the TS6
# board. BCSR stands for Board Control and Status Register.
# This space is treated as general I/O. Programming the
# following 2 registers describes how the MPC8260 will inter-
# operate with this memory space.
#
# History:
#
# Jan 9/99 jay
#
#########################################################################
init_bcsr:
#-------------------------------------------------------------------------
# Base Register 1 (BR1): Bank 1 is assigned to the Board Control and
# Status Registers (BCSRs). There are 3
# that resides on the MPC8260 TS6 board.
# The particulars are defined here.
#
# BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value
# represents the upper 17 bits of the base address.
#
# Bits 17-18 reserved. = 00
#
# PS (Port Size) = 11b = 32 bit port size
#
# DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# WP (Write Protect) = 0 = both read and write accesses are allowed
#
# MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
# for 60x bus Selected
#
# EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
# the memory controller
# according to MSEL.
#
# ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# DR (Delayed Read) = 0 = Normal operation.
#
# V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
addis r3,0,0x0450 # R3 holds the value temporarily
ori r3,r3,0x1801
#-------------------------------------------------------------------------
# Option Register 1 (OR1) for GPCM use: further BCSR definitions
#
# AM (Address Mask) = 0xFFFF +1b = We have masked the upper 17 bits which
# which defines a 32 Kbyte memory block.
#
# Bits 17-19 Reserved - set to 000.
#
# CSNT (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally.
#
# ACS (Address To Chip-Select Setup) = 00 = CS/ is output at the same
# time as the addr lines.
#
# Bit 23 Reserved - set to 0.
#
# SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state
#
# SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated
# internally by the memory
# controller unless GTA/ is
# asserted earlier externally.
#
# TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM.
#
# EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is
# generated by the memory
# controller
#
# Bit 31 Reserved - set to 0.
#-------------------------------------------------------------------------
addis r5,0,0xFFFF # R5 holds the value temporarily
ori r5,r5,0x8010
#------------------
# Write the values
#------------------
stw r5,CYGARC_REG_IMM_OR1(r4)
stw r3,CYGARC_REG_IMM_BR1(r4)
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_fpga_mem
#
# Description: This function programs Base Register 4 and Option Register 4
# designating bank 4 for the FPGA control space on the TS6
# board.
#
# History:
#
#
#########################################################################
init_fpga_mem:
#-------------------------------------------------------------------------
# Base Register 4 (BR4): Bank 4 is assigned to FPGA control memory map.
#
# BA (Base Address) = 0x0450+0b for a total of 17 address bits. This value
# represents the upper 17 bits of the base address.
#
# Bits 17-18 reserved. = 00
#
# PS (Port Size) = 11b = 32 bit port size
#
# DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# WP (Write Protect) = 0 = both read and write accesses are allowed
#
# MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
# for 60x bus Selected
#
# EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
# the memory controller
# according to MSEL.
#
# ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# DR (Delayed Read) = 0 = Normal operation.
#
# V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
addis r3,0,0x0450 # R3 holds the value temporarily
ori r3,r3,0x1801
#-------------------------------------------------------------------------
# Option Register 1 (OR1) for GPCM use: further BCSR definitions
#
# AM (Address Mask) = 0xFFFF +0b = We have masked the upper 16 bits which
# which defines a 64 Kbyte memory block.
#
# Bits 17-19 Reserved - set to 000.
#
# CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter cycle
# early. For now, put in all delay
# possible.
#
# ACS (Address To Chip-Select Setup) = 11 = CS/ is output one half clock
# after the addr lines.
#
# Bit 23 Reserved - set to 0.
#
# SCY (Cycle Length In Clocks) = 0000 = The SETA bit is set, therefore
# SCY is not used.
#
# SETA (External Transfer Acknowledge) = 1 = PSDVAL/ is generated
# by external logic, is this
# case, the FPGA.
#
# TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM.
#
# EHTR (Extended Hold Time On Read Accesses) = 1 = Eight idle cycle inserted
# between a read access from
# the current bank and
# next access.
#
# Bit 31 Reserved - set to 0.
#-------------------------------------------------------------------------
addis r5,0,0xFFFF # R5 holds the value temporarily
ori r5,r5,0x0E0E
#------------------
# Write the values
#------------------
stw r5,CYGARC_REG_IMM_OR4(r4)
stw r3,CYGARC_REG_IMM_BR4(r4)
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_cluster_bus
#
# Description: This function programs Base Register 8 and Option Register 8
# designating bank 8 for the Cluster Bus space on the TS6
# board.
#
# History:
#
#
#########################################################################
init_cluster_bus:
#-------------------------------------------------------------------------
# Base Register 8 (BR8): Bank 8 is assigned to Cluster Bus memory map.
#
# BA (Base Address) = 0xe000+0b for a total of 17 address bits. This value
# represents the upper 17 bits of the base address.
#
# Bits 17-18 reserved. = 00
#
# PS (Port Size) = 00b = 64 bit port size (use 64 bit port size)
# PS (Port Size) = 11b = 32 bit port size
#
# DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# WP (Write Protect) = 0 = both read and write accesses are allowed
#
# MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
# for 60x bus Selected
#
# EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
# the memory controller
# according to MSEL.
#
# ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# DR (Delayed Read) = 0 = Normal operation.
#
# V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
addis r3,0,0xE000 # R3 holds the value temporarily
ori r3,r3,0x0001
#-------------------------------------------------------------------------
# Option Register 8 (OR8) for GPCM use: further BCSR definitions
#
# AM (Address Mask) = 0xF000 +0b = We have masked the upper 4 bits which
# which defines a 256 Mbyte memory block.
#
# Bits 17-19 Reserved - set to 000.
#
# CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter cycle
# early. For now, put in all delay
# possible.
#
# ACS (Address To Chip-Select Setup) = 11 = CS/ is output one half clock
# after the addr lines.
#
# Bit 23 Reserved - set to 0.
#
# SCY (Cycle Length In Clocks) = 0000 = The SETA bit is set, therefore
# SCY is not used.
#
# SETA (External Transfer Acknowledge) = 1 = PSDVAL/ is generated
# by external logic, is this
# case, the FPGA.
#
# TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM.
#
# EHTR (Extended Hold Time On Read Accesses) = 1 = Eight idle cycle inserted
# between a read access from
# the current bank and
# next access.
#
# Bit 31 Reserved - set to 0.
#-------------------------------------------------------------------------
addis r5,0,0xF000 # R5 holds the value temporarily
ori r5,r5,0x0E0E
#------------------
# Write the values
#------------------
stw r5,CYGARC_REG_IMM_OR8(r4)
stw r3,CYGARC_REG_IMM_BR8(r4)
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_60x_sdram
#
# Description: This function programs the 64 Mbyte SDRAM DIMM on the TS6
# board. This memory functions as the RAM for the 603 core and
# is connected to the 60x bus. Base and Option Register 5 are
# used as well as the SDRAM Machine #1 and Chip Select #5.
#
# History:
#
# Apr /10/02 pfine Modified so that all 64 MBytes are addressable.
#
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -