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# - ESE (External Snoop Enable = 0 = [GPL/]/[IRQ1/] pin is IRQ1/
#
# - PBSE (Parity Byte Select Enable) = 0 = Parity byte select is disabled.
#
# - CDIS (Core DISable) = 0 = The PowerQUICCII CPU core is enabled.
#
# - DPPC (Data Parity Pins Configuration) = 10 =
#
# Gives the following pin meanings: DP(0)|RSRV/|EXT_BR2/ = RSRV/
# DP(1)|IRQ1/|EXT_BG2/ = IRQ1/
# DP(2)|TLBISYNC/|IRQ2/ = TLBISYNC/
# DP(3)|IRQ3/ = IRQ3/
# DP(4)|IRQ4/ = IRQ4/
# DP(5)|TBEN/|IRQ5 = TBEN/
# DP(6)|CSE(0)|IRQ6/ = CSE(0)
# DP(7)|CSE(1)|IRQ7/ = CSE(1)
#
# - L2CPC (L2 Cache Pins Configuration) = 00 =
#
# Gives the following pin meanings: CI/|BADDR(29)|IRQ2/ = CI/
# WT/|BADDR(30)|IRQ3/ = WT/
# L2_HIT/|IRQ4 = L2_HIT/
#
# CPU_BG/|BADDR(31)
# |IRQ5/ = CPU_BG/
#
# - LBPC (Local Bus Pins Configuration) = 00 =
#
# Local Bus pins function as local bus.
#
# - APPC (Address Parity Pins Configuration) = 11 =
#
# Gives the following pin meanings: MODCK1|AP(1)|TC(0) = -
# MODCK2|AP(2)|TC(1) = -
# MODCK3|AP(3)|TC(2) = -
# IRQ7/|APE/|INT_OUT/ = IRQ7/+INT_OUT/
# CS11/|AP(0) = -
#
# - CS10PC (Chip Select 10-pin Configuration) = 00 =
#
# CS10/|BCTL1/|DBG_DIS/ = CS10/
#
# - BCTLC (Buffer Control Configuration) = 00 =
#
# BCTL0 pin is used as W|R/ control. BCTL1 is used as OE/ control if
# BCTL1 was connected to its alternate pin.
#
# - MMR (Mask Masters Requests) = 00 = No masking on bus request lines.
#
# - LPBSE (Local Bus Parity Byte Select Enable) = 0
#
# Parity byte select is disabled.
#
# Bits 19-31 are reserved and set to 0.
#
#------------------------------------------------------------------------
#--------------------------------------------------------------------------
# Program the 60x Bus Transfer Error Status and Control Register 1. The
# details are as follows:
#
# - DMD (Data Errors Disable) = 1 =
#
# Disable all data errors on the 60x bus. Also parity single and double
# ECC error.
#
# - All other bits are either status or reserved bits. All reserved bits
# should be set to 0.
#--------------------------------------------------------------------------
addis r3,0,0x0000
ori r3,r3,0x4000
stw r3,CYGARC_REG_IMM_TESCR1(r4)
#--------------------------------------------------------------------------
# Program the Local Bus Transfer Error Status and Control Register 1. The
# details are as follows:
#
# - DMD (Data Errors Disable) = 1 =
#
# Disable parity errors on the Local bus.
#
# - All other bits are either status or reserved bits. All reserved bits
# should be set to 0.
#--------------------------------------------------------------------------
addis r3,0,0x0E30
ori r3,r3,0x0000
stw r3,CYGARC_REG_IMM_SIUMCR(r4)
# FIXME - What is this programming from??????
addis r3,0,0x0000
ori r3,r3,0x4000
stw r3,CYGARC_REG_IMM_LTESCR1(r4)
#-------------------------------------------------------------------------
# First, program the Memory Periodic Timer Prescaler Register (MPTPR).
# Finding the value to this ties in with the desired SDRAM Refresh
# Timer (PSRT) value and the required Refresh Command interval for
# refreshing each row. The Refresh Command interval is found by
# determining the number of rows on the SDRAM device. In this case
# its 4096 (12 bits to address rows). The "Refresh Period" value in the
# AC characteristic section of the data sheet is 64 msec. This value
# is divided by the number of rows to give the number of Refresh
# commands that needs to be sent in a 64 msec interval. This value
# is 64 msec/4096 = 15.625 usec.
# Due to probable contention from time to time with other memory
# controller bus requests, lets make the refresh command interval to be
# around 15.5 usec.
#
# Using the calculation found in the MPC8260 User Manual errata, the
# timer period is
#
# Timer Period = (PSRT + 1) * (MPTPR[PTP] + 1)
# ----------------------------
# Bus Frequency
#
# - Set PSRT = 16
# - Set MPTPR[PTP] = 40
# - Use 45 MHz as Bus Frequency
#
#
# - Timer Period = 15.489 usec
#
#
# The clock distribution block diagram looks like this:
#
# ---------- ------------- ----------- -------------
# | Clock | | MPT | | SDRAM | | Refresh |
# | Gen. |-----| Prescaler |---------| Refresh |----| Command |
# | 45 Mhz | ------------- | Timer | | Logic in |
# | on Ts6 | ----------- | Mem.Cont. |
# | Board | -------------
# -----------
#
#-------------------------------------------------------------------------
# addi r5,0,0x4000 # load 0x40 or 64 into the PTP field of MPTPR
addi r5,0,0x2800 # load 0x28 or 40 into the PTP field of MPTPR
sth r5,CYGARC_REG_IMM_MPTPR(r4) # store half word - bits[16-31]
#-----------------------
# return from init_siu
#-----------------------
bclr 20,0 # jump unconditionally to effective address in Link
# register
#########################################################################
# Function: init_memc
#
# Description:
#
# The following registers directly control the memory controllers
# operation:
#
# BR0-BR11 - Base Register Banks 0-11
# OR0-OR11 - Option Register Banks 0-11
# PSDMR - 60x bus SDRAM machine mode register
# LSDMR - Local bus SDRAM machine mode register
# MAMR - UPMA mode register
# MBMR - UPMB mode register
# MCMR - UPMC mode register
# MDR - Memory data register
# MAR - Memory address register
# MPTPR - Memory periodic timer pre-scaler register
# PURT - 60x bus assigned UPM refresh timer
# PSRT - 60x bus assigned SDRAM refresh timer
# LURT - Local Bus assigned UPM refresh timer
# LSRT - Local Bus assigned SDRAM refresh timer
#
# This example will program the following registers. The rest will remain at
# their default values.
#
# BR0 - Base Register for Flash Memory
# OR0 - Option Register for Flash Memory
# BR1 - Base Register for BCSR (Board Control and Status Registers)
# OR1 - Option Register for BCSR
# BR2 - Base Register for 60x SDRAM
# OR2 - Option Register for 60x SDRAM
# BR3 - Base Register for 60x Local Bus SDRAM
# OR3 - Option Register for 60x Local Bus SDRAM
# PSDMR - 60x bus SDRAM machine mode register
# LSDMR - Local bus SDRAM machine mode register
# MPTPR - Memory periodic timer pre-scaler register
# PSRT - 60x bus assigned SDRAM refresh timer
# LSRT - Local Bus assigned SDRAM refresh timer
#
#
# History:
#
#########################################################################
init_memc:
mfspr r30,CYGARC_REG_LR # Save the Link Register value. The link registers
# value will be restored so that this function
# can return to the calling address.
bl init_flash # 8 Mbyte of flash memory
bl init_fpga_mem # 64 KByte memory map for FPGA access
bl init_cluster_bus # 256 MByte Memory mapped for Tiger Sharc cluster bus
#ifdef MORE_FLASH
#endif
#if 0 // The Delphi TS6 Digital Board does not have BCSR
bl init_bcsr # Board Control and Status Registers
#endif
bl init_60x_sdram # Main 60x Bus SDRAM
#-----------------------
# return from init_memc
#-----------------------
mtspr CYGARC_REG_LR,r30 # restore original Link Register value
bclr 20,0 # jump unconditionally to effective address in Link
# register
############################################################################
# Function: init_flash
#
# Description: This function programs Base Register 0 and Option Register 0
# designating bank 0 for the 8Mbyte flash SIMM on the TS6
# board. Programming these two registers describes how the
# MPC8260 will inter-operate with this memory space and thus
# this memory device.
#
# History:
#
############################################################################
init_flash:
#-------------------------------------------------------------------------
# Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
# flash that resides on the MPC8260 TS6 board.
# The particulars are defined here.
#
# BA (Base Address) = 0xFF80+0b for a total of 17 address bits. This value
# represents the upper 17 bits of the base address.
#
# Bits 17-18 reserved. = 00
#
# PS (Port Size) = 11b = 32 bit port size
#
# DECC (Data Error Correction and Checking) = 00 = Data errors checking
# Disabled.
#
# WP (Write Protect) = 0 = both read and write accesses are allowed
#
# MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
# for 60x bus Selected
#
# EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
# the memory controller
# according to MSEL.
#
# ATOM (Atomic Operation) = 00 = The address space controlled by the
# memory controller bank is not used for
# atomic operations.
#
# DR (Delayed Read) = 0 = Normal operation.
#
# V (Valid Bit) = 1 = Valid bit set
#-------------------------------------------------------------------------
addis r3,0,0xFF80 # R3 holds the value temporarily
ori r3,r3,0x1801
#-------------------------------------------------------------------------
# Option Register 0 (OR0) for GPCM use: further flash definitions
#
# AM (Address Mask) = 0xFF80+0b = We have masked the upper 9 bits which
# defines a 8 Mbyte memory block.
#
# Bits 17-19 Reserved - set to 000.
#
# CSNT (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter
# of a clock early.
#
# ACS (Address To Chip-Select Setup) = 00 = CS/ is output the same time as
# the addr lines.
#
# Bit 23 Reserved - set to 0.
#
# SCY (Cycle Length In Clocks) = 0011 = Add a 3 clock cycle wait state
#
# SETA (External Transfer Acknowledge) = 0 = PSDVAL/ is generated
# internally by the memory
# controller unless GTA/ is
# asserted earlier externally.
#
# TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM.
#
# EHTR (Extended Hold Time On Read Accesses) = 1 =
#
# Extended hold time is generated by the memory controller. An idle
# clock cycle is inserted between a read access from the current bank
# and any write or read access to a different bank.
#
# Bit 31 Reserved - set to 0.
#-------------------------------------------------------------------------
addis r5,0,0xFF80 # R5 holds the value temporarily
ori r5,r5,0x0836
#------------------------------------------------------------------------
# It is important to note the order in which OR0 and BR0 are programmed.
# When coming out of reset and CS0 is the global chip select, OR0 MUST be
# programmed AFTER BR0. In all other cases BRx would be programmed after
# ORx.
#------------------------------------------------------------------------
#------------------
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