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	/*
	 *  SYSTEM CLOCK CONTROL REGISTER
	 *
	 *  COM   (1:2)   = 0
	 *  TBS   (6)     = 1
	 *  RTDIV (7)     = 0
	 *  RTSEL (8)     = 0
	 *  CRQEN (9)     = 0
	 *  PRQEN (10)    = 0
	 *  EBDF  (13:14) = 0
	 *  DFSYNC(17:18) = 0
	 *  DFBRG (19:20) = 0
	 *  DFNL  (21:23) = 0
	 *  DFNH  (24:26) = 0
	 */
	lwi	r3,0x02000000
	stw	r3,SCCR(r4)
	
	/*
	 *  The following sets up a 40MHz CPU clock.
	 *  I've seen 2 variations of MBX boards. One
	 *  uses a direct feed (1:1) 40MHz clock on
	 *  EXTCLK inputs. The other uses a 32KHz
	 *  oscillator on the OSCM inputs.
	 */
	lwz	r3,PLPRCR(r4)
	rlwinm	r3,r3,12,20,31
	cmpwi	r3,0
	beq     1f
	
	/*
	 *  PLL, LOW POWER, AND RESET CONTROL REGISTER
	 *
	 *  MF    (0:11)  = depends on source clock
	 *  SPLSS (16)    = 1
	 *  TEXPS (17)    = 1
	 *  TMIST (19)    = 1
	 *  CSRC  (21)    = 0
	 *  LPM   (22:23) = 0
	 *  CSR   (24)    = 0
	 *  LOLRE (25)    = 0
	 *  FIOPD (26)    = 0
	 */
	/*  MF    (0:11)  = 0x4c4 = 1220 = (40MHz/32.768KHz) */
#ifdef __50MHZ
	lwi	r3,0x5f50d000
#else
	lwi	r3,0x4c40d000
#endif
	b	2f
    1:
	/*  MF    (0:11)  = 0x000 = 1 = (1:1) */
	lwi	r3,0x0000d000
    2:
	stw	r3,PLPRCR(r4)

	# mask interrupt sources in the SIU
	lis	r2,0
	lwi	r3,CYGARC_REG_IMM_SIMASK
	stw	r2,0(r3)

	# set the decrementer to maxint
	lwi	r2,0
	not	r2,r2
	mtdec	r2
	
	# and enable the timebase and decrementer to make sure
	li	r2,1				# TBEnable and not TBFreeze
	lwi	r3,CYGARC_REG_IMM_TBSCR
	sth	r2,0(r3)

	LED( 8 ) # turn red led off

#ifdef CYG_HAL_STARTUP_ROM
	# move return address to where the ROM is
	mflr	r3
	andi.	r3,r3,0xffff
	oris	r3,r3,CYGMEM_REGION_rom>>16
	mtlr	r3
#endif

	blr
FUNC_END( hal_hardware_init )


#ifdef CYGPRI_DO_PROGRAM_UPMS
# -------------------------------------------------------------------------
# this table initializes the User Programmable Machine (UPM) nastiness
# in the QUICC to control DRAM timing.

__upmtbl_start:

#ifdef __25MHZ
	/* UPM contents for 25MHz clk. DRAM: EDO,4K,60ns */
	
	/* Single read. (offset 0 in upm RAM) */
        .long	0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst read. (offset 8 in upm RAM) */
        .long	0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
        .long	0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
        .long	0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Single write. (offset 18 in upm RAM) */
        .long	0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x33ff6c0f
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst write. (offset 20 in upm RAM) */
        .long	0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x03ff2c0c
        .long	0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
        .long	0x08ff2c00, 0x33ff6c0f, 0xffffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Refresh (offset 30 in upm RAM) */
        .long	0xc0ffec04, 0x07ffec04, 0x3fffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
	
	/* Exception. (offset 3c in upm RAM) */
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
#endif

#ifdef __33MHZ
	/* UPM contents for 33MHz clk. DRAM: EDO,4K,60ns */
	
	/* Single read. (offset 0 in upm RAM) */
        .long	0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst read. (offset 8 in upm RAM) */
        .long	0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
        .long	0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
        .long	0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Single write. (offset 18 in upm RAM) */
        .long	0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x33ff6c07
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst write. (offset 20 in upm RAM) */
        .long	0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x03ff2c0c
        .long	0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
        .long	0x08ff2c00, 0x33ff6c07, 0xffffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Refresh (offset 30 in upm RAM) */
        .long	0xc0ffec04, 0x03ffec04, 0x1fffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
	
	/* Exception. (offset 3c in upm RAM) */
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
#endif

#ifdef CYGPRI_USE_OLD_UPM_TABLES

	// BUT new tables received from motorola are further down

	// And I just discovered a good reason for using the NEW TABLES:
	// with the old tables, the cache zero-a-line command does not
	// work.  It only zeros the first 12 bytes of the line, not all 16.
	// This may be related to having the cache set up write-through, as
	// seems necessary to have it work on this platform.

#ifdef __40MHZ
	/* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
	
	/* Single read. (offset 0 in upm RAM) */
        .long	0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
        .long	0x03af2c08, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst read. (offset 8 in upm RAM) */
        .long	0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
        .long	0x03af2c08, 0x0caf2c04, 0x00af2c04, 0x03af2c08
        .long	0x0caf2c04, 0x00af2c04, 0x03af2c08, 0x0caf2c04
        .long	0x00af2c04, 0x03af2c08, 0xffffec07, 0xffffec07

	/* Single write. (offset 18 in upm RAM) */
        .long	0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
        .long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst write. (offset 20 in upm RAM) */
        .long	0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
        .long	0x0fff2c0c, 0x0cff2c00, 0x03ff2c0c, 0x0cff2c00
        .long	0x03ff2c0c, 0x0cff2c00, 0x33ff6c07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07

	/* Refresh (offset 30 in upm RAM) */
        .long	0xf0ffec04, 0x00ffec04, 0x0fffec04, 0x0fffec04
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
	
	/* Exception. (offset 3c in upm RAM) */
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
#endif

#ifdef __50MHZ
	/* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
	
	/* Single read. (offset 0 in upm RAM) */
	.long	0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
	.long	0x00af2c04, 0x0faf2c08, 0xffffec07, 0xffffec07

	/* Burst read. (offset 8 in upm RAM) */
	.long	0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
	.long	0x00af2c04, 0x0faf2c08, 0x0caf2c04, 0x00af2c04
	.long	0x0faf2c08, 0x0caf2c04, 0x00af2c04, 0x0faf2c08
	.long	0x0caf2c04, 0x00af2c04, 0x0faf2c08, 0xffffec07

	/* Single write. (offset 18 in upm RAM) */
	.long	0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
	.long	0x00ff2c00, 0xffffec07, 0xffffec07, 0xffffec07

	/* Burst write. (offset 20 in upm RAM) */
	.long	0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
	.long	0x00ff2c00, 0x0fff2c08, 0x0cff2c04, 0x00ff2c00
	.long	0x0fff2c00, 0x0cff2c04, 0x00ff2c00, 0x0fff2c08
	.long	0x0cff2c04, 0x00ff2c00, 0xffffec07, 0xffffec07

	/* Refresh (offset 30 in upm RAM) */
	.long	0xf0ffec04, 0xc0ffec04, 0x00ffec04, 0x0fffec04
	.long	0x1fffec07, 0xffffec07, 0xffffec07, 0xffffec07
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
		
	/* Exception. (offset 3c in upm RAM) */
	.long	0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
#endif

#else // !CYGPRI_USE_OLD_UPM_TABLES: use the NEW TABLES

	// for RAM startup or ROM application when NOT making a stub rom,
	// ie. CYGSEM_HAL_ROM_MONITOR not defined.

#ifdef __40MHZ
	/* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
	.long	0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x30af0c00
	.long	0xf1bf4805, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x03af0c08
	.long	0x0caf0c04, 0x03af0c08, 0x0caf0c04, 0x03af0c08
	.long	0x0caf0c04, 0x30af0c00, 0xf3bf4805, 0xffffc005
	.long	0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x33ff4804
	.long	0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
	.long	0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
	.long	0x0cff0c00, 0x33ff4804, 0xffffc005, 0xffffc005
	.long	0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
	.long	0x3fffc004, 0xffffc005, 0xffffc005, 0xffffc005
	.long	0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
#endif
	
#ifdef __50MHZ
	/* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
	
	.long	0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x10af0c04
	.long	0xf0af0c00, 0xf3bf4805, 0xffffc005, 0xffffc005

	.long	0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x00af0c04
	.long	0x07af0c08, 0x0caf0c04, 0x01af0c04, 0x0faf0c08
	.long	0x0caf0c04, 0x01af0c04, 0x0faf0c08, 0x0caf0c04
	.long	0x10af0c04, 0xf0afc000, 0xf3bf4805, 0xffffc005

	.long	0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x13ff4804
	.long	0xffffc004, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
	.long	0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
	.long	0x0cff0c00, 0x13ff4804, 0xffffc004, 0xffffc005
	.long	0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
	.long	0x1fffc004, 0xffffc004, 0xffffc005, 0xffffc005
	.long	0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005

	.long	0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
#endif
#endif	// OLD/NEW TABLES == CYGPRI_USE_OLD_UPM_TABLES or not.
	// depending on CYGSEM_HAL_ROM_MONITOR and whether RAM
	// start re-initializes.
	
__upmtbl_end:
#endif // CYGPRI_DO_PROGRAM_UPMS
	
FUNC_START(hal_mbx_set_led)
	andi.	r3,r3,0x0e
	lwi	r4,0xfa100001
	stb	r3,0(r4)
	blr
FUNC_END(hal_mbx_set_led)
	
FUNC_START(hal_mbx_flash_led)
	lwi	r4,0xfa100001
    1:	
	li	r5,10
	stb	r5,0(r4)
	
	lis	r5,10
	mtctr   r5
    2:	
	bdnz	2b

	li	r5,12
	stb	r5,0(r4)
	
	lis	r5,10
	mtctr   r5
    3:	
	bdnz	3b
	
	subi	r3,r3,1
	cmpwi	r3,0
	bge	1b

	li	r5,6
	stb	r5,0(r4)

	lis	r5,20
	mtctr   r5
    4:	
	bdnz	4b

	blr
FUNC_END(hal_mbx_flash_led)


#------------------------------------------------------------------------------
# end of mbx.S
12

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