📄 mpc8xxx.h
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volatile CYG_BYTE Rev_num[0x2];
volatile CYG_BYTE D_ptr[0x2];
volatile CYG_BYTE reserved_4[0x4];
volatile CYG_BYTE rand[0x4];
volatile CYG_BYTE i2c[0x2];
volatile CYG_BYTE idma4[0x2];
volatile CYG_BYTE reserved_5[0x500];
} standard;
} pram;
volatile CYG_BYTE reserved11[0x2000]; /* Reserved area */
volatile CYG_BYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */
volatile CYG_BYTE reserved12[0x4000]; /* Reserved area */
/* siu */
volatile CYG_WORD siu_siumcr; /* SIU Module Configuration Register */
volatile CYG_WORD siu_sypcr; /* System Protection Control Register */
volatile CYG_BYTE reserved13[0x6]; /* Reserved area */
volatile CYG_WORD16 siu_swsr; /* Software Service Register */
/* buses */
volatile CYG_BYTE reserved14[0x14]; /* Reserved area */
volatile CYG_WORD bcr; /* Bus Configuration Register */
volatile CYG_BYTE ppc_acr; /* Arbiter Configuration Register */
volatile CYG_BYTE reserved15[0x3]; /* Reserved area */
volatile CYG_WORD ppc_alrh; /* Arbitration level Register (First clients)*/
volatile CYG_WORD ppc_alrl; /* Arbitration Level Register (Next clients) */
volatile CYG_BYTE lcl_acr; /* LCL Arbiter Configuration Register */
volatile CYG_BYTE reserved16[0x3]; /* Reserved area */
volatile CYG_WORD lcl_alrh; /* LCL Arbitration level Register (First clients)*/
volatile CYG_WORD lcl_alrl; /* LCL Arbitration Level Register (Next clients) */
volatile CYG_WORD tescr1; /* PPC bus transfer error status control register 1 */
volatile CYG_WORD tescr2; /* PPC bus transfer error status control register 2 */
volatile CYG_WORD ltescr1; /* Local bus transfer error status control register 1 */
volatile CYG_WORD ltescr2; /* Local bus transfer error status control register 2 */
volatile CYG_WORD pdtea; /* PPC bus DMA Transfer Error Address */
volatile CYG_BYTE pdtem; /* PPC bus DMA Transfer Error MSNUM */
volatile CYG_BYTE reserved17[0x3]; /* Reserved area */
volatile CYG_WORD ldtea; /* PPC bus DMA Transfer Error Address */
volatile CYG_BYTE ldtem; /* PPC bus DMA Transfer Error MSNUM */
volatile CYG_BYTE reserved18[0xa3]; /* Reserved area */
/* memc */
struct mem_regs
{
volatile CYG_WORD memc_br; /* Base Register */
volatile CYG_WORD memc_or; /* Option Register */
} mem_regs[12];
volatile CYG_BYTE reserved19[0x8]; /* Reserved area */
volatile CYG_WORD memc_mar; /* Memory Address Register */
volatile CYG_BYTE reserved20[0x4]; /* Reserved area */
volatile CYG_WORD memc_mamr; /* Machine A Mode Register */
volatile CYG_WORD memc_mbmr; /* Machine B Mode Register */
volatile CYG_WORD memc_mcmr; /* Machine C Mode Register */
volatile CYG_WORD memc_mdmr; /* Machine D Mode Register */
volatile CYG_BYTE reserved21[0x4]; /* Reserved area */
volatile CYG_WORD16 memc_mptpr; /* Memory Periodic Timer Prescaler */
volatile CYG_BYTE reserved22[0x2]; /* Reserved area */
volatile CYG_WORD memc_mdr; /* Memory Data Register */
volatile CYG_BYTE reserved23[0x4]; /* Reserved area */
volatile CYG_WORD memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */
volatile CYG_WORD memc_lsdmr; /* Local Bus SDRAM machine Mode Registe */
volatile CYG_BYTE memc_purt; /* PowerPC Bus assigned UPM Refresh Timer */
volatile CYG_BYTE reserved24[0x3]; /* Reserved area */
volatile CYG_BYTE memc_psrt; /* PowerPC BusBus assigned SDRAM Refresh Timer */
volatile CYG_BYTE reserved25[0x3]; /* Reserved area */
volatile CYG_BYTE memc_lurt; /* Local Bus assigned UPM Refresh Timer */
volatile CYG_BYTE reserved26[0x3]; /* Reserved area */
volatile CYG_BYTE memc_lsrt; /* Local Bus assigned SDRAM Refresh Timer */
volatile CYG_BYTE reserved27[0x3]; /* Reserved area */
volatile CYG_WORD memc_immr; /* Internal Memory Map Register */
/* pci */
volatile CYG_WORD pcibr0; /* Base address+valid for PCI window 1 */
volatile CYG_WORD pcibr1; /* Base address+valid for PCI window 2 */
volatile CYG_BYTE reserved28[0x10]; /* Reserved area */
volatile CYG_WORD pcimsk0; /* Mask for PCI window 1 */
volatile CYG_WORD pcimsk1; /* Mask for PCI window 2 */
volatile CYG_BYTE reserved29[0x54]; /* Reserved area */
/* si_timers */
volatile CYG_WORD16 si_timers_tmcntsc; /* Time Counter Status and Control Register */
volatile CYG_BYTE reserved30[0x2]; /* Reserved area */
volatile CYG_WORD si_timers_tmcnt; /* Time Counter Register */
volatile CYG_WORD si_timers_tmcntsec; /* Time Counter Seconds*/
volatile CYG_WORD si_timers_tmcntal; /* Time Counter Alarm Register */
volatile CYG_BYTE reserved31[0x10]; /* Reserved area */
volatile CYG_WORD16 si_timers_piscr; /* Periodic Interrupt Status and Control Reg. */
volatile CYG_BYTE reserved32[0x2]; /* Reserved area */
volatile CYG_WORD si_timers_pitc; /* Periodic Interrupt Count Register */
volatile CYG_WORD si_timers_pitr; /* Periodic Interrupt Timer Register */
volatile CYG_BYTE reserved33[0x54]; /* Reserved area */
/* test module registers */
volatile CYG_WORD tstmhr;
volatile CYG_WORD tstmlr;
volatile CYG_WORD16 tster;
volatile CYG_BYTE reserved34[0x156]; /* Reserved area */
/* pci, part 2 */
volatile CYG_WORD pci_pci; /* PCI Configuration space - offset 0x10400 */
volatile CYG_BYTE reserved_pci404[0x10430-0x10404];
volatile CYG_WORD pci_omisr; /* Outbound interrupt status */
volatile CYG_WORD pci_omimr; /* Outbound interrupt mask */
volatile CYG_WORD reserved_pci438;
volatile CYG_WORD reserved_pci43C;
volatile CYG_WORD pci_ifqpr; /* Inbound FIFO queue */
volatile CYG_WORD pci_ofqpr; /* Outbound FIFO queue */
volatile CYG_WORD reserved_pci448;
volatile CYG_WORD reserved_pci44C;
volatile CYG_WORD pci_imr; /* Inbound message register #0 */
volatile CYG_WORD pci_imr1; /* Inbound message register #1 */
volatile CYG_WORD pci_omr0; /* Outbound message register #0 */
volatile CYG_WORD pci_omr1; /* Outbound message register #1 */
volatile CYG_WORD pci_odr; /* Outbound doorbell */
volatile CYG_WORD reserved_pci464;
volatile CYG_WORD pci_idr; /* Inbound doorbell */
volatile CYG_BYTE reserved_pci46C[0x10480-0x1046C];
volatile CYG_WORD pci_imisr; /* Inbound message interrupt status */
volatile CYG_WORD pci_imimr; /* Inbound message interrupt mask */
volatile CYG_BYTE reserved_pci488[0x104A0-0x10488];
volatile CYG_WORD pci_ifhpr; /* Inbound free FIFO head */
volatile CYG_WORD reserved_pci4A4;
volatile CYG_WORD pci_iftpr; /* Inbound free FIFO tail */
volatile CYG_WORD reserved_pci4AC;
volatile CYG_WORD pci_iphpr; /* Inbound post FIFO head */
volatile CYG_WORD reserved_pci4B4;
volatile CYG_WORD pci_iptpr; /* Inbound post FIFO tail */
volatile CYG_WORD reserved_pci4BC;
volatile CYG_WORD pci_ofhpr; /* Outbound free FIFO head */
volatile CYG_WORD reserved_pci4C4;
volatile CYG_WORD pci_oftpr; /* Outbound free FIFO tail */
volatile CYG_WORD reserved_pci4CC;
volatile CYG_WORD pci_ophpr; /* Outbound post FIFO head */
volatile CYG_WORD reserved_pci4D4;
volatile CYG_WORD pci_optpr; /* Outbound post FIFO tail */
volatile CYG_WORD reserved_pci4DC;
volatile CYG_WORD reserved_pci4E0;
volatile CYG_WORD pci_mucr; /* Message unit control */
volatile CYG_BYTE reserved_pci4E8[0x104F0-0x104E8];
volatile CYG_WORD pci_qbar; /* Queue base address */
volatile CYG_BYTE reserved_pci4F4[0x10500-0x104F4];
volatile CYG_WORD pci_dmamr0; /* DMA #0 - mode */
volatile CYG_WORD pci_dmasr0; /* DMA #0 - status */
volatile CYG_WORD pci_dmacdar0; /* DMA #0 - current descriptor address */
volatile CYG_WORD reserved_pci50C;
volatile CYG_WORD pci_dmasar0; /* DMA #0 - source address */
volatile CYG_WORD reserved_pci514;
volatile CYG_WORD pci_dmadar0; /* DMA #0 - destination address */
volatile CYG_WORD reserved_pci51C;
volatile CYG_WORD pci_dmabcr0; /* DMA #0 - byte count */
volatile CYG_WORD pci_dmandar0; /* DMA #0 - next descriptor */
volatile CYG_BYTE reserved_pci528[0x10580-0x10528];
volatile CYG_WORD pci_dmamr1; /* DMA #1 - mode */
volatile CYG_WORD pci_dmasr1; /* DMA #1 - status */
volatile CYG_WORD pci_dmacdar1; /* DMA #1 - current descriptor address */
volatile CYG_WORD reserved_pci58C;
volatile CYG_WORD pci_dmasar1; /* DMA #1 - source address */
volatile CYG_WORD reserved_pci594;
volatile CYG_WORD pci_dmadar1; /* DMA #1 - destination address */
volatile CYG_WORD reserved_pci59C;
volatile CYG_WORD pci_dmabcr1; /* DMA #1 - byte count */
volatile CYG_WORD pci_dmandar1; /* DMA #1 - next descriptor */
volatile CYG_BYTE reserved_pci5A8[0x10600-0x105A8];
volatile CYG_WORD pci_dmamr2; /* DMA #2 - mode */
volatile CYG_WORD pci_dmasr2; /* DMA #2 - status */
volatile CYG_WORD pci_dmacdar2; /* DMA #2 - current descriptor address */
volatile CYG_WORD reserved_pci60C;
volatile CYG_WORD pci_dmasar2; /* DMA #2 - source address */
volatile CYG_WORD reserved_pci614;
volatile CYG_WORD pci_dmadar2; /* DMA #2 - destination address */
volatile CYG_WORD reserved_pci61C;
volatile CYG_WORD pci_dmabcr2; /* DMA #2 - byte count */
volatile CYG_WORD pci_dmandar2; /* DMA #2 - next descriptor */
volatile CYG_BYTE reserved_pci628[0x10680-0x10628];
volatile CYG_WORD pci_dmamr3; /* DMA #3 - mode */
volatile CYG_WORD pci_dmasr3; /* DMA #3 - status */
volatile CYG_WORD pci_dmacdar3; /* DMA #3 - current descriptor address */
volatile CYG_WORD reserved_pci68C;
volatile CYG_WORD pci_dmasar3; /* DMA #3 - source address */
volatile CYG_WORD reserved_pci694;
volatile CYG_WORD pci_dmadar3; /* DMA #3 - destination address */
volatile CYG_WORD reserved_pci69C;
volatile CYG_WORD pci_dmabcr3; /* DMA #3 - byte count */
volatile CYG_WORD pci_dmandar3; /* DMA #3 - next descriptor */
volatile CYG_BYTE reserved_pci6A8[0x10800-0x106A8];
volatile CYG_WORD pci_potar0; /* PCI outbound translation address #0 */
volatile CYG_WORD reserved_pci804;
volatile CYG_WORD pci_potbar0; /* PCI outbound base address #0 */
volatile CYG_WORD reserved_pci80C;
volatile CYG_WORD pci_pocmr0; /* PCI outbound comparison mask #0 */
volatile CYG_WORD reserved_pci814;
volatile CYG_WORD pci_potar1; /* PCI outbound translation address #1 */
volatile CYG_WORD reserved_pci81C;
volatile CYG_WORD pci_potbar1; /* PCI outbound base address #1 */
volatile CYG_WORD reserved_pci824;
volatile CYG_WORD pci_pocmr1; /* PCI outbound comparison mask #1 */
volatile CYG_WORD reserved_pci82C;
volatile CYG_WORD pci_potar2; /* PCI outbound translation address #2 */
volatile CYG_WORD reserved_pci834;
volatile CYG_WORD pci_potbar2; /* PCI outbound base address #2 */
volatile CYG_WORD reserved_pci83C;
volatile CYG_WORD pci_pocmr2; /* PCI outbound comparison mask #2 */
volatile CYG_BYTE reserved_pci844[0x10878-0x10844];
volatile CYG_WORD pci_ptcr; /* Discard timer control */
volatile CYG_WORD pci_gpcr; /* General purpose control */
volatile CYG_WORD pci_gcr; /* PCI general control */
volatile CYG_WORD pci_esr; /* Error status */
volatile CYG_WORD pci_emr; /* Error mask */
volatile CYG_WORD pci_ecr; /* Error control */
volatile CYG_WORD pci_eacr; /* Error address capture */
volatile CYG_WORD reserved_pci894;
volatile CYG_WORD pci_edcr; /* Error data capture */
volatile CYG_WORD reserved_pci89C;
volatile CYG_WORD pci_eccr; /* Error control */
volatile CYG_BYTE reserved_pci8D0[0x108D0-0x108A4];
volatile CYG_WORD pci_pitar1; /* Inbound address translation #1 */
volatile CYG_WORD reserved_pci8D8;
volatile CYG_WORD pci_pibar1; /* Inbound address base #1 */
volatile CYG_WORD reserved_pci8E0;
volatile CYG_WORD pci_picmr1; /* Inbound comparison mask #1 */
volatile CYG_WORD reserved_pci8E8;
volatile CYG_WORD pci_pitar0; /* Inbound address translation #0 */
volatile CYG_WORD reserved_pci8F0;
volatile CYG_WORD pci_pibar0; /* Inbound address base #0 */
volatile CYG_WORD reserved_pci8F8;
volatile CYG_WORD pci_picmr0; /* Inbound comparison mask #0 */
volatile CYG_WORD reserved_pci900;
volatile CYG_WORD pci_cfg_addr; /* Indirect access to PCI config space - address ptr */
volatile CYG_WORD pci_cfg_data; /* Indirect access to PCI config space - data */
volatile CYG_WORD pci_int_ack; /* Used to acknowledge PCI interrupts */
volatile CYG_BYTE reserved_pci0C00[0x10C00-0x1090C];
/* ic */
volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register - offset 0x10C00 */
volatile CYG_BYTE reserved36[0x2]; /* Reserved area */
volatile CYG_BYTE ic_sivec; /* CP Interrupt Vector Register */
volatile CYG_BYTE reserved36a[0x3]; /* Reserved area */
volatile CYG_WORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */
volatile CYG_WORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */
volatile CYG_WORD ic_siprr; /* SIU Interrupt Priority Register */
volatile CYG_WORD ic_scprr_h; /* Interrupt Priority Register (HIGH) */
volatile CYG_WORD ic_scprr_l; /* Interrupt Priority Register (LOW) */
volatile CYG_WORD ic_simr_h; /* Interrupt Mask Register (HIGH) */
volatile CYG_WORD ic_simr_l; /* Interrupt Mask Register (LOW) */
volatile CYG_WORD ic_siexr; /* External Interrupt Control Register */
volatile CYG_BYTE reserved37[0x58]; /* Reserved area */
/* clocks */
volatile CYG_WORD clocks_sccr; /* System Clock Control Register */
volatile CYG_BYTE reserved38[0x4]; /* Reserved area */
volatile CYG_WORD clocks_scmr; /* System Clock Mode Register */
volatile CYG_BYTE reserved39[0x4]; /* Reserved area */
volatile CYG_WORD clocks_rsr; /* Reset Status Register */
volatile CYG_WORD clocks_rmr; /* Reset Mode Register */
volatile CYG_BYTE reserved40[0x68]; /* Reserved area */
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