mpc8xxx.h

开放源码实时操作系统源码.

#ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
#define CYGONCE_HAL_PPC_QUICC2_MPC8260_H

//==========================================================================
//
//      mpc8260.h
//
//      PowerPC QUICC2 register definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Red Hat
// Contributors: hmt, gthomas
// Date:         1999-06-08
// Purpose:      PowerPC QUICC2 definitions
// Description:  PowerPC QUICC2 definitions
// Usage:        THIS IS NOT AN EXTERNAL API
//               This file is in the include dir to share it between
//               QUICCII serial code and MPC8260 initialization code.
//               #include <cyg/hal/mpc8260.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <cyg/hal/plf_regs.h>           // For IMM base

#define DPRAM_SMC1_OFFSET 0x2000
#define DPRAM_SMC2_OFFSET 0x2100
#define DPRAM_BD_OFFSET   0x2200

#define _Packed 
#define _PackedType __attribute__((packed))

/******************************************************************************
*
*  PARAMETER RAM (PRAM) FOR EACH PERIPHERAL
*  
*  Each subsection contains protocol-specific PRAM for each peripheral,
*  followed by the PRAM common to all protocols for that peripheral.  These 
*  structs are used as needed in the main MPC8260 memory map structure.  Note 
*  that different modes of operation will require the use of different PRAM 
*  structs, and that certain structs may overlay and conflict with the use of 
*  other PRAM areas.  Consult the MPC8260 User Manual for details as to what
*  is unavailable when certain protocols are run on certain peripherals.
*
******************************************************************************/
                          


/*---------------------------------------------------------------------------*/
/*                   SERIAL COMMUNICATION CONTROLLER (SCC)                 */
/*---------------------------------------------------------------------------*/

/*----------*/
/* SCC HDLC */
/*----------*/

typedef _Packed struct 
{
    CYG_BYTE    reserved1[4]; /* Reserved area */
    CYG_WORD    c_mask;       /* CRC constant */
    CYG_WORD    c_pres;       /* CRC preset */
    CYG_WORD16   disfc;        /* discarded frame counter */
    CYG_WORD16   crcec;        /* CRC error counter */
    CYG_WORD16   abtsc;        /* abort sequence counter */
    CYG_WORD16   nmarc;        /* nonmatching address rx cnt */
    CYG_WORD16   retrc;        /* frame transmission counter. */
                           /* For FCC this area is reserved.*/
    CYG_WORD16   mflr;         /* maximum frame length reg */
    CYG_WORD16   max_cnt;      /* maximum length counter */
    CYG_WORD16   rfthr;        /* received frames threshold */
    CYG_WORD16   rfcnt;        /* received frames count */
    CYG_WORD16   hmask;        /* user defined frm addr mask */
    CYG_WORD16   haddr1;       /* user defined frm address 1 */
    CYG_WORD16   haddr2;       /* user defined frm address 2 */
    CYG_WORD16   haddr3;       /* user defined frm address 3 */
    CYG_WORD16   haddr4;       /* user defined frm address 4 */
    CYG_WORD16   tmp;          /* temp */
    CYG_WORD16   tmp_mb;       /* temp */
} _PackedType t_HdlcScc_Pram;

 
/*--------------*/
/* SCC Ethernet */
/*--------------*/

typedef _Packed struct 
{
    CYG_WORD    c_pres;      /* CRC preset */
    CYG_WORD    c_mask;      /* CRC constant mask*/
    CYG_WORD    crcec;       /* CRC error counter */
    CYG_WORD    alec;        /* alignment error counter */
    CYG_WORD    disfc;       /* discarded frame counter */
    CYG_WORD16   pads;        /* Short frame pad character. */
    CYG_WORD16   ret_lim;     /* Retry limit threshold. */
    CYG_WORD16   ret_cnt;     /* Retry limit counter. */
    CYG_WORD16   mflr;        /* maximum frame length reg */
    CYG_WORD16   minflr;      /* minimum frame length reg */
    CYG_WORD16   maxd1;       /* max DMA1 length register. */
    CYG_WORD16   maxd2;       /* max DMA2 length register. */
    CYG_WORD16   maxd;        /* Rx max DMA. */
    CYG_WORD16   dma_cnt;     /* Rx DMA counter. */
    CYG_WORD16   max_b;       /* max buffer descriptor byte count. */
    CYG_WORD16   gaddr1;      /* group address filter */
    CYG_WORD16   gaddr2;      /* group address filter */
    CYG_WORD16   gaddr3;      /* group address filter */
    CYG_WORD16   gaddr4;      /* group address filter */
    CYG_WORD    tbuf0_data0; /* Saved area 0, current frame. */
    CYG_WORD    tbuf0_data1; /* Saved area 1, current frame. */
    CYG_WORD    tbuf0_rba0;
    CYG_WORD    tbuf0_crc;
    CYG_WORD16   tbuf0_bcnt;
    CYG_WORD16   paddr1_h;    /* physical address (MSB) */
    CYG_WORD16   paddr1_m;    /* physical address */
    CYG_WORD16   paddr1_l;    /* physical address (LSB) */
    CYG_WORD16   p_per;       /* persistence */
    CYG_WORD16   rfbd_ptr;    /* Rx first BD pointer. */
    CYG_WORD16   tfbd_ptr;    /* Tx first BD pointer. */
    CYG_WORD16   tlbd_ptr;    /* Tx last BD pointer. */
    CYG_WORD    tbuf1_data0; /* Saved area 0, next frame. */
    CYG_WORD    tbuf1_data1; /* Saved area 1, next frame. */
    CYG_WORD    tbuf1_rba0;
    CYG_WORD    tbuf1_crc;
    CYG_WORD16   tbuf1_bcnt;
    CYG_WORD16   tx_len;      /* tx frame length counter */
    CYG_WORD16   iaddr1;      /* individual address filter. */
    CYG_WORD16   iaddr2;      /* individual address filter.  */
    CYG_WORD16   iaddr3;      /* individual address filter. */
    CYG_WORD16   iaddr4;      /* individual address filter.  */
    CYG_WORD16   boff_cnt;    /* back-off counter */
    CYG_WORD16   taddr_h;     /* temp address (MSB) */
    CYG_WORD16   taddr_m;     /* temp address */
    CYG_WORD16   taddr_l;     /* temp address (LSB) */
} _PackedType t_EnetScc_Pram;

/*----------*/
/* SCC UART */
/*----------*/

typedef _Packed struct 
{
    CYG_BYTE       reserved1[8];   /* Reserved area */
    CYG_WORD16      max_idl;        /* maximum idle characters */
    CYG_WORD16      idlc;           /* rx idle counter (internal) */
    CYG_WORD16      brkcr;          /* break count register */
    CYG_WORD16      parec;          /* Rx parity error counter */
    CYG_WORD16      frmec;          /* Rx framing error counter */
    CYG_WORD16      nosec;          /* Rx noise counter */
    CYG_WORD16      brkec;          /* Rx break character counter */
    CYG_WORD16      brkln;          /* Receive break length */
    CYG_WORD16      uaddr1;         /* address character 1 */
    CYG_WORD16      uaddr2;         /* address character 2 */
    CYG_WORD16      rtemp;          /* temp storage */
    CYG_WORD16      toseq;          /* Tx out of sequence char */
    CYG_WORD16      cc[8];          /* Rx control characters */
    CYG_WORD16      rccm;           /* Rx control char mask */
    CYG_WORD16      rccr;           /* Rx control char register */
    CYG_WORD16      rlbc;           /* Receive last break char */
} _PackedType t_UartScc_Pram;


/*-----------------*/
/* SCC Transparent */
/*-----------------*/

typedef _Packed struct  
{
    CYG_WORD    c_mask;     /* CRC constant */
    CYG_WORD    c_pres;     /* CRC preset */
} _PackedType t_TransScc_Pram;


/*------------*/
/* SCC Bisync */
/*------------*/

typedef _Packed struct  
{
   CYG_BYTE    reserved1[4];     /* Reserved area */
   CYG_WORD crcc;       /* CRC Constant Temp Value */
   CYG_WORD16   prcrc;         /* Preset Receiver CRC-16/LRC */
   CYG_WORD16   ptcrc;         /* Preset Transmitter CRC-16/LRC */
   CYG_WORD16   parec;         /* Receive Parity Error Counter */
   CYG_WORD16   bsync;         /* BISYNC SYNC Character */
   CYG_WORD16   bdle;       /* BISYNC DLE Character */
   CYG_WORD16   cc[8];         /* Rx control characters */
   CYG_WORD16   rccm;       /* Receive Control Character Mask */
} _PackedType t_BisyncScc_Pram;


/*-----------------*/
/* SCC Common PRAM */
/*-----------------*/

typedef _Packed struct 
{
    CYG_WORD16   rbase;      /* RX BD base address */
    CYG_WORD16   tbase;      /* TX BD base address */
    CYG_BYTE    rfcr;       /* Rx function code */
    CYG_BYTE    tfcr;       /* Tx function code */
    CYG_WORD16   mrblr;      /* Rx buffer length */
    CYG_WORD    rstate;     /* Rx internal state */
    CYG_WORD    rptr;       /* Rx internal data pointer */
    CYG_WORD16   rbptr;      /* rb BD Pointer */
    CYG_WORD16   rcount;     /* Rx internal byte count */
    CYG_WORD    rtemp;      /* Rx temp */
    CYG_WORD    tstate;     /* Tx internal state */
    CYG_WORD    tptr;       /* Tx internal data pointer */
    CYG_WORD16   tbptr;      /* Tx BD pointer */
    CYG_WORD16   tcount;     /* Tx byte count */
    CYG_WORD    ttemp;      /* Tx temp */
    CYG_WORD    rcrc;       /* temp receive CRC */
    CYG_WORD    tcrc;       /* temp transmit CRC */
    union 
    {
       t_HdlcScc_Pram    h;
       t_EnetScc_Pram    e;
       t_UartScc_Pram    u;
       t_TransScc_Pram   t;
       t_BisyncScc_Pram  b;