var_cache.h

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                  : "I" (5) /* %0 ==> r5 */,          \
                    "I" (6) /* %1 ==> r6 */,          \
                    "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);

//-----------------------------------------------------------------------------
// Data cache line control

// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )

// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
    CYG_MACRO_START                                             \
    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
    cyg_int32 __size = (cyg_int32) (_size_);                    \
    while (__size > 0) {                                        \
        asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
        __base += HAL_DCACHE_LINE_SIZE;                         \
        __size -= HAL_DCACHE_LINE_SIZE;                         \
    }                                                           \
    CYG_MACRO_END


// Invalidate cache lines in the given range without writing to memory.
// NOTE: The errata for the 603e processor indicates use of the dcbf
// command as the dcbi command will only invalidate modified blocks.
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                \
    CYG_MACRO_START                                             \
    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
    cyg_int32 __size = (cyg_int32) (_size_);                    \
    while (__size > 0) {                                        \
        asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
        __base += HAL_DCACHE_LINE_SIZE;                         \
        __size -= HAL_DCACHE_LINE_SIZE;                         \
    }                                                           \
    CYG_MACRO_END

// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE( _base_ , _size_ )                     \
    CYG_MACRO_START                                             \
    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
    cyg_int32 __size = (cyg_int32) (_size_);                    \
    while (__size > 0) {                                        \
        asm volatile ("dcbst 0,%0;sync;" : : "r" (__base));     \
        __base += HAL_DCACHE_LINE_SIZE;                         \
        __size -= HAL_DCACHE_LINE_SIZE;                         \
    }                                                           \
    CYG_MACRO_END

// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )

// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )

// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )

//-----------------------------------------------------------------------------
// Global control of Instruction cache

// Enable the instruction cache
#define HAL_ICACHE_ENABLE()                 \
    CYG_MACRO_START                         \
    cyg_uint32 tmp1, tmp2;                  \
    asm volatile (                          \
        "mfspr %1, %2;"                     \
        "li %0, 0x4000;"                    \
        "rlwimi %1,%0,1,16,16;"             \
        "sync;"                             \
        "isync;"                            \
        "mtspr %2,%1;"                      \
        "isync;"                            \
        "sync;"                             \
        : "=r" (tmp1), "=r" (tmp2)          \
        : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
    CYG_MACRO_END

// Disable the instruction cache
#define HAL_ICACHE_DISABLE()                          \
    CYG_MACRO_START                         \
    cyg_uint32 tmp1, tmp2;                  \
    asm volatile (                          \
        "mfspr %1, %2;"                     \
        "li %0, 0x0;"                       \
        "rlwimi %1,%0,0,16,16;"             \
        "sync;"                             \
        "isync;"                            \
        "mtspr %2,%1;"                      \
        "isync;"                            \
        "sync;"                             \
        : "=r" (tmp1), "=r" (tmp2)          \
        : "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */); \
    CYG_MACRO_END

// Invalidate the entire cache
#if 1
#define HAL_ICACHE_INVALIDATE_ALL()                   \
    CYG_MACRO_START                                   \
    cyg_uint32 tmp1, tmp2;                            \
    asm volatile ("sync;"                             \
                  "mfspr %0, %2;"                     \
                  "ori   %1, %0, 0x8000;"             \
                  "mtspr %2, %1;"                     \
                  "isync;"                            \
                  "sync;"                             \
                  "ori   %1, %1, 0x0800;"             \
                  "mtspr %2, %1;"                     \
                  "isync;"                            \
                  "sync;"                             \
                  "mtspr %2, %0;"                     \
                  "isync;"                            \
                  "sync;"                             \
                  : "=r" (tmp1), "=r" (tmp2)          \
                  : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
    CYG_MACRO_END
#else
#define HAL_ICACHE_INVALIDATE_ALL()                   \
    CYG_MACRO_START                                   \
    cyg_uint32 tmp1, tmp2;                            \
    asm volatile ("sync;"                             \
                  "mfspr %0, %2;"                     \
                  "ori   %0, %0, 0x0800;"             \
                  "isync;"                            \
                  "mtspr %2, %0;"                     \
                  "li    %1, 0;"                      \
                  "rlwimi %0,%1,0,20,20;"             \
                  "isync;"                            \
                  "mtspr %2, %0;"                     \
                  "isync;"                            \
                  "sync;"                             \
                  : "=r" (tmp1), "=r" (tmp2)          \
                  : "I" (CYGARC_REG_HID0) /* %3 ==> HID0 */);\
    CYG_MACRO_END
#endif
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC()                             \
    HAL_ICACHE_INVALIDATE_ALL()


// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_)                          \
    asm volatile ("mfspr  %0, %1;"                              \
                  "rlwinm %0,%0,17,31,31;"                      \
                  : "=r" (_state_) : "I" (CYGARC_REG_HID0))


// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)

// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)

// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)

// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL()                       \
    asm volatile ("isync;"                            \
                  "mfspr %0, %2;"                     \
                  "oris  %1, 0,0xFFFF;"               \
                  "ori   %1,%1,0xDFFF;"               \
                  "and   %0,%0,%1;"                   \
                  "isync;"                            \
                  "mtspr %2,%0;"                      \
                  "isync;"                            \
                  "sync;"                             \
                  : /* No output */                   \
                  : "I" (5) /* %0 ==> r5 */,          \
                    "I" (6) /* %1 ==> r6 */,          \
                    "I" (CYGARC_REG_HID0) /* %2 ==> HID0 */);

//-----------------------------------------------------------------------------
// Instruction cache line control

// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )

//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h