viper.s

开放源码实时操作系统源码.

#define MAMR_PTA 116
#endif        
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 63)
#define PLPRCR_PTX 0x01004000 // (62.7MHz/3.6864MHz)-1
#define MAMR_PTA 123
#endif        
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED == 100)
#define PLPRCR_PTX 0x01A04000 // (99.53MHz/3.6864MHz)-1
#define MAMR_PTA 194
#endif        
//#define MAMR_PTA (((((((PLPRCR_PTX+1)*3686400)*625)/10000000)+31)/32)&0xFF)
#endif                
        lwi     r3,0x00802114|(MAMR_PTA<<24)
        stw	r3,MAMR(r4)
        stw	r3,MBMR(r4)

	/*
	 * Base Register initialization.
	 */

       	/* BOOT ROM */
#ifdef CYGHWR_HAL_POWERPC_VIPER_I  // Old board layout
        lwi	r3,0xFE000401	# 8-bit, GPCM
        lwi	r5,0xFF800774   # 7 wait states, up to 8MB
#else
        lwi	r3,0xFE000801	# 16-bit, GPCM
        lwi	r5,0xFF800774   # 7 wait states, up to 8MB
#endif                
        stw	r3,BR0(r4)
        stw	r5,OR0(r4)

	/* Misc I/O, 16 bit port */
        lwi	r3,0xFA100801
        lwi	r5,0xFFFF8730
        stw	r3,BR2(r4)
        stw	r5,OR2(r4)

	/* ONBOARD DRAM */
        lwi	r3,0x00000081	# 32-bit, UPMA
        lwi	r5,0xFF800E00
        stw	r3,BR1(r4)
        stw	r5,OR1(r4)

	/* DRAM DIMM BANK1 */
        lwi	r3,0x00000080	# 32-bit, UPMA, INVALID
        lwi	r5,0xFFFF87FC
        stw	r3,BR3(r4)
        stw	r5,OR3(r4)

#if 0        
	/* NVRAM */
        lwi	r3,0xfa000401	# 8-bit, GPCM
        lwi	r5,0xffe00930
        stw	r3,BR4(r4)
        stw	r5,OR4(r4)

	/* PCI BRIDGE MEM/IO */
        lwi	r3,0x80000001	# 32-bit, GPCM
        lwi	r5,0xa0000108
        stw	r3,BR5(r4)
        stw	r5,OR5(r4)

	/* PCI BRIDGE REGISTERS */
        lwi	r3,0xfa210001	# 32-bit, GPCM
        lwi	r5,0xffff0108
        stw	r3,BR6(r4)
        stw	r5,OR6(r4)

	/* FLASH */
        lwi	r3,0xfc000001	# 32-bit, GPCM
        lwi	r5,0xff800940
        stw	r3,BR7(r4)
        stw	r5,OR7(r4)
#endif
        
	/*
	 *  SYSTEM CLOCK CONTROL REGISTER
// Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
// 	Field Reserved (bit 0) = 0
// 	Field COM (bits 1-2) = 0
// 	Field Reserved (bits 3-5) = 0
// 	Field TBS (bit 6) = 0
// 	Field RTDIV (bit 7) = 0
// 	Field RTSEL (bit 8) = 0
// 	Field CRQEN (bit 9) = 1
// 	Field PRQEN (bit 10) = 0
// 	Field Reserved (bits 11-12) = 0
// 	Field EBDF (bits 13-14) = 0
// 	Field Reserved (bits 15-16) = 0
// 	Field DFSYNC (bits 17-18) = 0
// 	Field DFBRG (bits 19-20) = 0
// 	Field DFNL (bits 21-23) = 0
// 	Field DFNH (bits 24-26) = 0
// 	Field Reserved (bits 27-31) = 0
	 */
#if (CYGHWR_HAL_POWERPC_BOARD_SPEED > 63)
	lwi	r3,0x00420000  // Bus divide by 2
#else
	lwi	r3,0x00400000
#endif        
	stw	r3,SCCR(r4)
        
	LED( 0x03 )

	/*
	 *  PLL, LOW POWER, AND RESET CONTROL REGISTER
// Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
// 	Field MF (bits 0-11) = 12
// 	Field Reserved (bits 12-15) = 0
// 	Field SPLSS (bit 16) = 0
// 	Field TEXPS (bit 17) = 1
// 	Field Reserved (bit 18) = 0
// 	Field TMIST (bit 19) = 0
// 	Field Reserved (bit 20) = 0
// 	Field CSRC (bit 21) = 0
// 	Field LPM (bits 22-23) = 0
// 	Field CSR (bit 24) = 0
// 	Field LOLRE (bit 25) = 0
// 	Field FIOPD (bit 26) = 0
// 	Field Reserved (bits 27-31) = 0
	 */
        lwi     r3,PLPRCR_PTX
	stw	r3,PLPRCR(r4)

	LED(0xE0)
	lwi	r3,0x40000
	mtctr	r3
10:	nop
	bdnz	10b
	LED(0xE1)

	/* SDRAM Initialization Sequence, UPMA, CS1 */
	li	r3,0
	stw	r3,MAR(r4)

	lwi 	r3,0x80002115;	/* run precharge from loc 21 (0x15) */
  	stw	r3,MCR(r4)

	lwi	r3,0x80002830;	/* run refresh 8 times */
   	stw	r3,MCR(r4)
	
	lwi	r3,0x88;	/* MR 88 for high range */
   	stw	r3,MAR(r4)

       	lwi	r3,0x80002116;	/* run MRS pattern from loc 22 (0x16) */
   	stw	r3,MCR(r4)

	# mask interrupt sources in the SIU
	lis	r2,0
	lwi	r3,CYGARC_REG_IMM_SIMASK
	stw	r2,0(r3)

	# set the decrementer to maxint
	lwi	r2,0
	not	r2,r2
	mtdec	r2
	
	# and enable the timebase and decrementer to make sure
	li	r2,1				# TBEnable and not TBFreeze
	lwi	r3,CYGARC_REG_IMM_TBSCR
	sth	r2,0(r3)

	LED( 8 ) 

#ifdef CYG_HAL_STARTUP_ROM
	# move return address to where the ROM is
	mflr	r3
        lwi     r4,0x00FFFFFF        // CAUTION!! Assumes only low 16M for ROM
        and     r3,r3,r4
	oris	r3,r3,CYGMEM_REGION_rom>>16
	mtlr	r3
#endif

#ifdef CYG_HAL_STARTUP_ROMRAM
        // Copy image from ROM to RAM
        LED(0x10)
        mflr    r3              
        lwi     r4,0xFE000000
        lwi     r5,0x01FFFFFF   // ROM/FLASH base
        and     r3,r3,r5        // segment relative
        lwi     r6,_hal_hardware_init_done
        mtlr    r6
        sub     r6,r3,r6        // Absolute address
        add     r6,r6,r4        // FLASH address
        lwi     r7,0            // where to copy to
        lwi     r8,__ram_data_end
10:     lwz     r5,0(r6)
        stw     r5,0(r7)
        addi    r6,r6,4
        addi    r7,r7,4
        cmplw   r7,r8
        bne     10b
        LED(0x20)
#endif                

	blr
FUNC_END( hal_hardware_init )


#ifdef CYGPRI_DO_PROGRAM_UPMS
# -------------------------------------------------------------------------
# this table initializes the User Programmable Machine (UPM) nastiness
# in the QUICC to control DRAM timing.

__upmtbl_start:
// single read   (offset 0x00 in upm ram)
       .long   0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00
       .long   0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04
// burst read    (offset 0x08 in upm ram)
       .long   0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00
       .long   0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44
       .long   0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35
       .long   0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35
// single write  (offset 0x18 in upm ram)
       .long   0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47
       .long   0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// burst write   (offset 0x20 in upm ram)
       .long   0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
       .long   0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// refresh       (offset 0x30 in upm ram)
       .long   0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// exception     (offset 0x3C in upm ram)
       .long   0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
__upmtbl_end:
#endif // CYGPRI_DO_PROGRAM_UPMS
	
FUNC_START(hal_viper_set_led)
	lwi	r4,0xFA100018
	stb	r3,0(r4)
	lwi	r5,_hold_led
	stw	r3,0(r5)
	blr
FUNC_END(hal_viper_set_led)
	.data
_hold_led:	
	.long	0
	.text	
	
FUNC_START(hal_viper_get_led)
	lwi	r5,_hold_led
	lwz	r3,0(r5)
	blr
FUNC_END(hal_viper_get_led)
	
FUNC_START(hal_viper_flash_led)
	lwi	r4,0xFA100018
    1:	
	li	r5,10
	stb	r5,0(r4)
	
	lis	r5,10
	mtctr   r5
    2:	
	bdnz	2b

	li	r5,12
	stb	r5,0(r4)
	
	lis	r5,10
	mtctr   r5
    3:	
	bdnz	3b
	
	subi	r3,r3,1
	cmpwi	r3,0
	bge	1b

	li	r5,6
	stb	r5,0(r4)

	lis	r5,20
	mtctr   r5
    4:	
	bdnz	4b

	blr
FUNC_END(hal_viper_flash_led)


#------------------------------------------------------------------------------
# end of viper.S