var_regs.h

开放源码实时操作系统源码.

#define CYGARC_REG_MI_CTR_CIDEF   0x20000000

#define CYGARC_REG_MD_CTR         792
#define CYGARC_REG_MD_CTR_CIDEF   0x20000000
#define CYGARC_REG_MD_CTR_WTDEF   0x10000000

//--------------------------------------------------------------------------
// Internal Memory Map.
#define CYGARC_REG_IMMR            638  // internal memory map base register
#define CYGARC_REG_IMMR_BASEMASK   0xffff0000 // imm base location mask (rw)
#define CYGARC_REG_IMMR_PARTNUM    0x0000ff00 // part number mask (ro)
#define CYGARC_REG_IMMR_MASKNUM    0x000000ff // mask number mask (ro)

#ifndef CYGARC_REG_IMM_BASE        // Can be defined by platform
#define CYGARC_REG_IMM_BASE        0xfa200000 // the internal memory map base
#endif

// CP Microcode Revision Number
#define CYGARC_REG_REV_NUM         ((CYGARC_REG_IMM_BASE)+0x3cb0)

// system protection control
#define CYGARC_REG_IMM_SYPCR       ((CYGARC_REG_IMM_BASE)+0x004)
#define CYGARC_REG_IMM_SYPCR_SWTC_MASK 0xffff0000
#define CYGARC_REG_IMM_SYPCR_BMT_MASK  0x0000ff00
#define CYGARC_REG_IMM_SYPCR_BME       0x00000080
#define CYGARC_REG_IMM_SYPCR_SWF       0x00000008
#define CYGARC_REG_IMM_SYPCR_SWE       0x00000004
#define CYGARC_REG_IMM_SYPCR_SWRI      0x00000002
#define CYGARC_REG_IMM_SYPCR_SWP       0x00000001

// interrupt pend register
#define CYGARC_REG_IMM_SIPEND      ((CYGARC_REG_IMM_BASE)+0x010)
#define CYGARC_REG_IMM_SIPEND_IRQ0 0x80000000 // irq0 is bit 0...

// interrupt mask
#define CYGARC_REG_IMM_SIMASK      ((CYGARC_REG_IMM_BASE)+0x014)
#define CYGARC_REG_IMM_SIMASK_IRQ0 0x80000000 // ... irq n is bit n*2

// interrupt edge level mask
#define CYGARC_REG_IMM_SIEL        ((CYGARC_REG_IMM_BASE)+0x018)
#define CYGARC_REG_IMM_SIEL_IRQ0   0x80000000

// interrupt vector
#define CYGARC_REG_IMM_SIVEC       ((CYGARC_REG_IMM_BASE)+0x01c)

// memory controller
#define CYGARC_REG_IMM_BR0         ((CYGARC_REG_IMM_BASE)+0x100)
#define CYGARC_REG_IMM_OR0         ((CYGARC_REG_IMM_BASE)+0x104)
#define CYGARC_REG_IMM_BR1         ((CYGARC_REG_IMM_BASE)+0x108)
#define CYGARC_REG_IMM_OR1         ((CYGARC_REG_IMM_BASE)+0x10c)
#define CYGARC_REG_IMM_BR2         ((CYGARC_REG_IMM_BASE)+0x110)
#define CYGARC_REG_IMM_OR2         ((CYGARC_REG_IMM_BASE)+0x114)
#define CYGARC_REG_IMM_BR3         ((CYGARC_REG_IMM_BASE)+0x118)
#define CYGARC_REG_IMM_OR3         ((CYGARC_REG_IMM_BASE)+0x11c)
#define CYGARC_REG_IMM_BR4         ((CYGARC_REG_IMM_BASE)+0x120)
#define CYGARC_REG_IMM_OR4         ((CYGARC_REG_IMM_BASE)+0x124)
#define CYGARC_REG_IMM_BR5         ((CYGARC_REG_IMM_BASE)+0x128)
#define CYGARC_REG_IMM_OR5         ((CYGARC_REG_IMM_BASE)+0x12c)
#define CYGARC_REG_IMM_BR6         ((CYGARC_REG_IMM_BASE)+0x130)
#define CYGARC_REG_IMM_OR6         ((CYGARC_REG_IMM_BASE)+0x134)
#define CYGARC_REG_IMM_BR7         ((CYGARC_REG_IMM_BASE)+0x138)
#define CYGARC_REG_IMM_OR7         ((CYGARC_REG_IMM_BASE)+0x13c)

#define CYGARC_REG_IMM_BR_BA_MASK  0xffff8000 // base address
#define CYGARC_REG_IMM_BR_AT_MASK  0x00007000 // address type
#define CYGARC_REG_IMM_BR_PS_8     0x00000400 // port size 8 bits
#define CYGARC_REG_IMM_BR_PS_16    0x00000800 // port size 16 bits
#define CYGARC_REG_IMM_BR_PS_32    0x00000000 // port size 32 bits
#define CYGARC_REG_IMM_BR_PARE     0x00000200 // parity enable 
#define CYGARC_REG_IMM_BR_WP       0x00000100 // write protect  
#define CYGARC_REG_IMM_BR_MS_GPCM  0x00000000 // machine select G.P.C.M
#define CYGARC_REG_IMM_BR_MS_UPMA  0x00000080 // machine select U.P.M.A
#define CYGARC_REG_IMM_BR_MS_UPMB  0x000000c0 // machine select U.P.M.B
#define CYGARC_REG_IMM_BR_V        0x00000001 // valid bit

#define CYGARC_REG_IMM_OR_AM     0xffff8000 // address mask
#define CYGARC_REG_IMM_OR_ATM    0x00007000 // address type mask
#define CYGARC_REG_IMM_OR_CSNT   0x00000800 // GPCM:chip select negation time
#define CYGARC_REG_IMM_OR_SAM    0x00000800 // UPMx:start address multiplex
#define CYGARC_REG_IMM_OR_ACS_0  0x00000000 // GPCM:CS output immediately
#define CYGARC_REG_IMM_OR_ACS_4  0x00000400 // GPCM:CS output 1/4 clock later
#define CYGARC_REG_IMM_OR_ACS_2  0x00000600 // GPCM:CS output 1/2 clock later
#define CYGARC_REG_IMM_OR_G5LA   0x00000400 // UPMx:general-purpose line 5 A
#define CYGARC_REG_IMM_OR_G5LS   0x00000200 // UPMx:general-purpose line 5 S
#define CYGARC_REG_IMM_OR_BI     0x00000100 // burst inhibit
#define CYGARC_REG_IMM_OR_SCY_MASK 0x000000f0 // cycle length in clocks
#define CYGARC_REG_IMM_OR_SCY_SHIFT 4
#define CYGARC_REG_IMM_OR_SETA     0x00000008 // external transfer ack
#define CYGARC_REG_IMM_OR_TRLX     0x00000004 // timing relaxed
#define CYGARC_REG_IMM_OR_EHTR     0x00000002 // extended hold time on read

// timebase status and control
#define CYGARC_REG_IMM_TBSCR       ((CYGARC_REG_IMM_BASE)+0x200) 
#define CYGARC_REG_IMM_TBSCR_REFA  0x0080 // reference interrupt status A
#define CYGARC_REG_IMM_TBSCR_REFB  0x0040 // reference interrupt status B
#define CYGARC_REG_IMM_TBSCR_REFAE 0x0008 // reference interrupt enable A
#define CYGARC_REG_IMM_TBSCR_REFBE 0x0004 // reference interrupt enable B
#define CYGARC_REG_IMM_TBSCR_TBF   0x0002 // timebase freeze
#define CYGARC_REG_IMM_TBSCR_TBE   0x0001 // timebase enable
#define CYGARC_REG_IMM_TBSCR_IRQ0  0x8000 // highest interrupt level
#define CYGARC_REG_IMM_TBSCR_IRQMASK 0xff00 // irq priority mask

// timebase reference register 0
#define CYGARC_REG_IMM_TBREF0      ((CYGARC_REG_IMM_BASE)+0x204)
// timebase reference register 1
#define CYGARC_REG_IMM_TBREF1      ((CYGARC_REG_IMM_BASE)+0x208)

// real time clock
#define CYGARC_REG_IMM_RTCSC       ((CYGARC_REG_IMM_BASE)+0x220)
#define CYGARC_REG_IMM_RTCSC_SEC   0x0080 // once per second interrupt
#define CYGARC_REG_IMM_RTCSC_ALR   0x0040 // alarm interrupt
#define CYGARC_REG_IMM_RTCSC_38K   0x0010 // source select
#define CYGARC_REG_IMM_RTCSC_SIE   0x0008 // second interrupt enable
#define CYGARC_REG_IMM_RTCSC_ALE   0x0004 // alarm interrupt enable
#define CYGARC_REG_IMM_RTCSC_RTF   0x0002 // real time clock freeze
#define CYGARC_REG_IMM_RTCSC_RTE   0x0001 // real time clock enable
#define CYGARC_REG_IMM_RTCSC_IRQ0  0x8000 // highest interrupt level
#define CYGARC_REG_IMM_RTCSC_IRQMASK 0xff00 // irq priority mask

// periodic interrupt status & ctrl
#define CYGARC_REG_IMM_PISCR       ((CYGARC_REG_IMM_BASE)+0x240)
#define CYGARC_REG_IMM_PISCR_PS    0x0080 // periodic interrupt status
#define CYGARC_REG_IMM_PISCR_PIE   0x0004 // periodic interrupt enable
#define CYGARC_REG_IMM_PISCR_PITF  0x0002 // periodic interrupt timer freeze
#define CYGARC_REG_IMM_PISCR_PTE   0x0001 // periodic timer enable
#define CYGARC_REG_IMM_PISCR_IRQ0  0x8000 // highest interrupt level
#define CYGARC_REG_IMM_PISCR_IRQMASK 0xff00 // irq priority mask

// periodic interrupt timer count
#define CYGARC_REG_IMM_PITC        ((CYGARC_REG_IMM_BASE)+0x244)
#define CYGARC_REG_IMM_PITC_COUNT_SHIFT 16 // count is stored in bits 0-15

// system clock control
#define CYGARC_REG_IMM_SCCR        ((CYGARC_REG_IMM_BASE)+0x280)
#define CYGARC_REG_IMM_SCCR_TBS    0x02000000 // timebase source
#define CYGARC_REG_IMM_SCCR_RTDIV  0x01000000 // rtc clock divide
#define CYGARC_REG_IMM_SCCR_RTSEL  0x00800000 // rtc clock select

// CPM interrupt vector register
#define CYGARC_REG_IMM_CIVR        ((CYGARC_REG_IMM_BASE)+0x930)
#define CYGARC_REG_IMM_CIVR_IACK   0x0001 // set this to update register
#define CYGARC_REG_IMM_CIVR_VECTOR_SHIFT 11 // vector is at bits 0-4

// CPM interrupt configuration reg
#define CYGARC_REG_IMM_CICR        ((CYGARC_REG_IMM_BASE)+0x940)
#define CYGARC_REG_IMM_CICR_IEN    0x00000080      // interrupt enable
#define CYGARC_REG_IMM_CICR_IRQMASK 0x0000e000     // irq priority mask
#define CYGARC_REG_IMM_CICR_IRQ_SHIFT 13

// CPM interrupt in-pending register
#define CYGARC_REG_IMM_CIPR        ((CYGARC_REG_IMM_BASE)+0x944)
// CPM interrupt mask register
#define CYGARC_REG_IMM_CIMR        ((CYGARC_REG_IMM_BASE)+0x948)
// CPM interrupt in-service register
#define CYGARC_REG_IMM_CISR        ((CYGARC_REG_IMM_BASE)+0x94C)


#define CYGARC_SIU_PRIORITY_LOW    7 // the lowest irq priority
#define CYGARC_SIU_PRIORITY_HIGH   0 // the highest irq priority

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//-----------------------------------------------------------------------------
// Development Support.
#define CYGARC_REG_DER             149

#define CYGARC_REG_ICTRL           158  // instruction support control reg
#define CYGARC_REG_ICTRL_SERSHOW   0x00000000 // serialized, show cycles
#define CYGARC_REG_ICTRL_NOSERSHOW 0x00000007 //non-serialized&no show cycles

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define DER             CYGARC_REG_DER

#define ICTRL           CYGARC_REG_ICTRL
#define ICTRL_SERSHOW   CYGARC_REG_ICTRL_SERSHOW
#define ICTRL_NOSERSHOW CYGARC_REG_ICTRL_NOSERSHOW
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//-----------------------------------------------------------------------------
#endif // ifdef CYGONCE_HAL_VAR_REGS_H
// End of var_regs.h