var_regs.h

开放源码实时操作系统源码.

#ifndef CYGONCE_HAL_VAR_REGS_H
#define CYGONCE_HAL_VAR_REGS_H

//==========================================================================
//
//      var_regs.h
//
//      PowerPC 8xx variant CPU definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov, gthomas
// Date:         2000-02-04
// Purpose:      Provide MPC8xx register definitions
// Description:  Provide MPC8xx register definitions
//               The short difinitions (sans CYGARC_REG_) are exported only
//               if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
// Usage:        Included via the acrhitecture register header:
//               #include <cyg/hal/ppc_regs.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <cyg/hal/plf_regs.h>

//--------------------------------------------------------------------------
// Instruction cache control.
#define CYGARC_REG_IC_CST          560
#define CYGARC_REG_IC_ADR          561
#define CYGARC_REG_IC_DAT          562

#define CYGARC_REG_IC_CMD_CE       0x02000000      // cache enable
#define CYGARC_REG_IC_CMD_CD       0x04000000      // cache disable
#define CYGARC_REG_IC_CMD_LL       0x06000000      // load & lock
#define CYGARC_REG_IC_CMD_UL       0x08000000      // unlock line
#define CYGARC_REG_IC_CMD_UA       0x0a000000      // unlock all
#define CYGARC_REG_IC_CMD_IA       0x0c000000      // invalidate all

#define CYGARC_REG_IC_ADR_SETID_SHIFT 4            // set id is bits 21-27
#define CYGARC_REG_IC_ADR_WAY0     0x00000000      // select way0
#define CYGARC_REG_IC_ADR_WAY1     0x00001000      // select way1

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define IC_CST          CYGARC_REG_IC_CST
#define IC_ADR          CYGARC_REG_IC_ADR
#define IC_DAT          CYGARC_REG_IC_DAT

#define IC_CMD_CE       CYGARC_REG_IC_CMD_CE
#define IC_CMD_CD       CYGARC_REG_IC_CMD_CD
#define IC_CMD_LL       CYGARC_REG_IC_CMD_LL
#define IC_CMD_UL       CYGARC_REG_IC_CMD_UL
#define IC_CMD_UA       CYGARC_REG_IC_CMD_UA
#define IC_CMD_IA       CYGARC_REG_IC_CMD_IA

#define IC_ADR_SETID_SHIFT CYGARC_REG_IC_ADR_SETID_SHIFT
#define IC_ADR_WAY0        CYGARC_REG_IC_ADR_WAY0
#define IC_ADR_WAY1        CYGARC_REG_IC_ADR_WAY1
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// Data cache control.
#define CYGARC_REG_DC_CST          568
#define CYGARC_REG_DC_ADR          569
#define CYGARC_REG_DC_DAT          570

#define CYGARC_REG_DC_CMD_CE       0x02000000      // cache enable
#define CYGARC_REG_DC_CMD_CD       0x04000000      // cache disable
#define CYGARC_REG_DC_CMD_LL       0x06000000      // lock line
#define CYGARC_REG_DC_CMD_UL       0x08000000      // unlock line
#define CYGARC_REG_DC_CMD_UA       0x0a000000      // unlock all
#define CYGARC_REG_DC_CMD_IA       0x0c000000      // invalidate all
#define CYGARC_REG_DC_CMD_FL       0x0e000000      // flush line
#define CYGARC_REG_DC_CMD_SW       0x01000000      // set writethrough
#define CYGARC_REG_DC_CMD_CW       0x03000000      // clear writethrough
#define CYGARC_REG_DC_CMD_SS       0x05000000      // set little endian swap
#define CYGARC_REG_DC_CMD_CS       0x07000000      // clear little endian swap

#define CYGARC_REG_DC_ADR_SETID_SHIFT 4            // set id is bits 21-27
#define CYGARC_REG_DC_ADR_WAY0     0x00000000      // select way0
#define CYGARC_REG_DC_ADR_WAY1     0x00001000      // select way1

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define DC_CST             CYGARC_REG_DC_CST
#define DC_ADR             CYGARC_REG_DC_ADR
#define DC_DAT             CYGARC_REG_DC_DAT

#define DC_CMD_CE          CYGARC_REG_DC_CMD_CE
#define DC_CMD_CD          CYGARC_REG_DC_CMD_CD
#define DC_CMD_LL          CYGARC_REG_DC_CMD_LL
#define DC_CMD_UL          CYGARC_REG_DC_CMD_UL
#define DC_CMD_UA          CYGARC_REG_DC_CMD_UA
#define DC_CMD_IA          CYGARC_REG_DC_CMD_IA
#define DC_CMD_FL          CYGARC_REG_DC_CMD_FL
#define DC_CMD_SW          CYGARC_REG_DC_CMD_SW
#define DC_CMD_CW          CYGARC_REG_DC_CMD_CW
#define DC_CMD_SS          CYGARC_REG_DC_CMD_SS
#define DC_CMD_CS          CYGARC_REG_DC_CMD_CS

#define DC_ADR_SETID_SHIFT CYGARC_REG_DC_ADR_SETID_SHIFT
#define DC_ADR_WAY0        CYGARC_REG_DC_ADR_WAY0
#define DC_ADR_WAY1        CYGARC_REG_DC_ADR_WAY1
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// MMU control.
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define M_CASID         793             // current address space id register

#define MI_CTR          784             // instruction MMU control
#define MI_EPN          787             // instruction MMU effective page num
#define MI_TWC          789             // instruction MMU tablewalk count
#define MI_RPN          790             // instruction MMU real page num
#define MI_DCAM         816             // instruction MMU CAM read
#define MI_DRAM0        817             // instruction MMU RAM read 0
#define MI_DRAM1        818             // instruction MMU RAM read 1

#define MI_EPN_EPNMASK  0xfffff000      // effective page no mask
#define MI_EPN_EV       0x00000200      // entry valid

#define MI_RPN_RPNMASK  0xfffff000      // real page no mask
#define MI_RPN_PPRWRW   0x000008f0      // page protection (rw/rw, page valid)
#define MI_RPN_LPS      0x0000000C      // large page size
#define MI_RPN_SH       0x00000004      // shared page (1 = no ASID cmp)
#define MI_RPN_CI       0x00000002      // cache inhibited
#define MI_RPN_V        0x00000001      // entry valid

#define MI_TWC_PS8MB    0x0000000c      // page size = 8MB
#define MI_TWC_G        0x00000010      // guarded
#define MI_TWC_WT       0x00000002      // writethrough
#define MI_TWC_V        0x00000001      // entry valid

#define MI_CTR_INDX_SHIFT 8             // the ITLB_INDX starts at bit 23

#define MD_CTR          792             // data MMU control
#define MD_EPN          795             // data MMU effective page num
#define MD_TWC          797             // data MMU tablewalk count
#define MD_RPN          798             // data MMU real page num
#define MD_DCAM         824             // data MMU CAM read
#define MD_DRAM0        825             // data MMU RAM read 0
#define MD_DRAM1        826             // data MMU RAM read 1

#define MD_RPN_CHANGED  0x00000100      // page changed

#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

#define CYGARC_REG_MI_CTR         784