aeb_misc.c

开放源码实时操作系统源码.

    // Enable timer
    iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_HIGH;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
    _period = period;
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
                             99,           // Priority
                             0,            // Data item passed to interrupt handler
                             aeb_abort_isr,
                             0,
                             &abort_interrupt_handle,
                             &abort_interrupt);
    cyg_drv_interrupt_attach(abort_interrupt_handle);
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
#endif
#ifdef _TIMERS_TESTING
    aeb_setup_timer1(period/10);
#endif
}

void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
    _period = period;
}

void hal_clock_read(cyg_uint32 *pvalue)
{
    cyg_uint32 value;
    cyg_uint8 reg;
    do {
        HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL,
                        TIMER_CTL_RW_LATCH|TIMER_CTL_SC_CTR0);
        HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB
        value = reg;
        HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB
        value |= (reg << 8);
    } while (value <= 2);  // Hardware malfunction?
    *pvalue = _period - (value & 0xFFFF);   // Note: counter is only 16 bits
                                            // and decreases
}

void hal_hardware_init(void)
{
    // Any hardware/platform initialization that needs to be done.
    // Set all unknowns as edge triggered
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR0,
                     ICTL_ICR0_CH0_HL_AL|ICTL_ICR0_CH0_EL_ET|
                     ICTL_ICR0_CH1_HL_AL|ICTL_ICR0_CH1_EL_ET|
                     ICTL_ICR0_CH2_HL_AL|ICTL_ICR0_CH2_EL_ET|
                     ICTL_ICR0_CH3_HL_AL|ICTL_ICR0_CH3_EL_ET|
                     ICTL_ICR0_CH4_HL_AL|ICTL_ICR0_CH4_EL_ET|
                     ICTL_ICR0_CH5_HL_AL|ICTL_ICR0_CH5_EL_ET);
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR1,
                     ICTL_ICR1_CH6_HL_AL|
                     ICTL_ICR1_CH7_HL_AL|
                     ICTL_ICR1_CH8_HL_AL);
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF);  // CLear all interrupts
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000);  // All disabled
    // Clear and initialize cache
    HAL_UCACHE_INVALIDATE_ALL();
    HAL_UCACHE_ENABLE();

    // Set up eCos/ROM interfaces
    hal_if_init();
}

//
// This routine is called to respond to a hardware interrupt (IRQ).  It
// should interrogate the hardware and return the IRQ vector number.

int hal_IRQ_handler(void)
{
    // Do hardware-level IRQ handling
    int irq_status, vector;
    HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status);
    for (vector = 0;  vector < 16;  vector++) {
        if (irq_status & (1<<vector)) return vector;
    }
    return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
}

//
// Interrupt control
//

void hal_interrupt_mask(int vector)
{
    cyg_uint32 mask, old_mask;
    HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
    old_mask = mask;
    mask &= ~(1<<vector);
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
}

#if 0
void hal_interrupt_status(void)
{
    int irq_status, irq_enable, ipr_value, timer_value;
    cyg_uint8 reg;
    HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB
    timer_value = reg;
    HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB
    timer_value |= (reg << 8);
    HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status);
    HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, irq_enable);
    HAL_READ_UINT32(CYG_DEVICE_ICTL_IPR, ipr_value);
    diag_printf("Interrupt: IRQ: %x.%x.%x, Timer: %x\n", irq_status,
                irq_enable, ipr_value, timer_value);
}
#endif

void hal_interrupt_unmask(int vector)
{
    cyg_uint32 mask, old_mask;
    HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
    old_mask = mask;
    mask |= (1<<vector);
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
}

void hal_interrupt_acknowledge(int vector)
{
    HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, (1<<vector));
}

void hal_interrupt_configure(int vector, int level, int up)
{
//    diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up);
}

void hal_interrupt_set_level(int vector, int level)
{
//    diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level);
}

void hal_show_IRQ(int vector, int data, int handler)
{
    //    diag_printf("IRQ - vector: %x, data: %x, handler: %x\n", vector,
    //                  data, handler);
}

#ifdef _TIMERS_TESTING
#include <cyg/hal/drv_api.h>            // HAL ISR support
static cyg_interrupt timer1_interrupt;
static cyg_handle_t  timer1_interrupt_handle;
static cyg_uint32    timer1_count;

// This ISR is called only for the high speed timer under test
static int
aeb_timer1_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
{
    cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_TIMER1);
    timer1_count++;
    return 0;  // No need to run DSR
}

static void
aeb_setup_timer1(cyg_uint32 period)
{
    cyg_uint32 iocr;

    // Set counter GATE input low (0) to halt counter while it's being setup
    HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr);
    iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);

    // Scale timer0 clock
    HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16);

    // Initialize counter, mode 2 = rate generator
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, 
                    TIMER_CTL_TYPE_BIN|
                    TIMER_CTL_MODE_RG|
                    TIMER_CTL_RW_BOTH|
                    TIMER_CTL_SC_CTR1);
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF));        // LSB
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB
    // Enable timer
    iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1,
                             99,             // Priority
                             0,              // Data item passed to interrupt handler
                             aeb_timer1_isr,
                             0,
                             &timer1_interrupt_handle,
                             &timer1_interrupt);
    cyg_drv_interrupt_attach(timer1_interrupt_handle);
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1);
}
#endif

//-----------------------------------------------------------------------------
// Reset board (definitions from watchdog file aeb1.cxx)

// Register definitions
#define CYGARC_REG_WATCHDOG_BASE        0xFFFFAC00
#define CYGARC_REG_WATCHDOG_WDCTLR      (CYGARC_REG_WATCHDOG_BASE+0x30)
#define CYGARC_REG_WATCHDOG_WDCNTR      (CYGARC_REG_WATCHDOG_BASE+0x34)

// Control register bits
#define CYGARC_REG_WATCHDOG_WDCTLR_EN        0x01 // enable
#define CYGARC_REG_WATCHDOG_WDCTLR_RSP_NMF   0x00 // non-maskable fiq
#define CYGARC_REG_WATCHDOG_WDCTLR_RSP_ER    0x04 // external reset
#define CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR    0x06 // system reset
#define CYGARC_REG_WATCHDOG_WDCTLR_FRZ       0x08 // lock enable bit
#define CYGARC_REG_WATCHDOG_WDCTLR_TOP_MASK  0x70 // time out period

#define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17    0x00 // 2^17
#define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17_P  5242880 // = 5.2ms

#define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25    0x40 // 2^25
#define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25_P  1342177300 // = 1.3421773s

void
hal_aeb_reset(void)
{
    // Clear the watchdog counter.
    HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0);

    // Enable the watchdog with the smallest timeout.
    HAL_WRITE_UINT8(CYGARC_REG_WATCHDOG_WDCTLR, 
                    (CYGARC_REG_WATCHDOG_WDCTLR_TOP_17
                     | CYGARC_REG_WATCHDOG_WDCTLR_FRZ
                     | CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR
                     | CYGARC_REG_WATCHDOG_WDCTLR_EN));

    // Wait for it...
    for(;;);
}

/*------------------------------------------------------------------------*/
// EOF hal_misc.c