📄 hal_cache.h
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#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors:hmt, jskov
// Travis C. Furrer <furrer@mit.edu>
// Tom Chase <tomc@dtccom.com>
// Date: 2005-05-10
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_mmu.h>
//-----------------------------------------------------------------------------
// Cache dimensions
#if defined(CYGPKG_HAL_ARM_ARM9_ARM920T)
# define HAL_ICACHE_SIZE 0x4000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 64
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x4000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 64
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
# define HAL_ICACHE_SIZE 0x2000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 64
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x2000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 64
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM925T)
# define HAL_ICACHE_SIZE 0x4000
# define HAL_ICACHE_LINE_SIZE 16
# define HAL_ICACHE_WAYS 2
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x2000
# define HAL_DCACHE_LINE_SIZE 16
# define HAL_DCACHE_WAYS 2
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
// must flush everything manually
# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ)
# define HAL_ICACHE_SIZE 0x4000
# define HAL_ICACHE_LINE_SIZE 32
# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x2000
# define HAL_DCACHE_LINE_SIZE 32
# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
#define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
# define HAL_ICACHE_SIZE 0x1000
# define HAL_ICACHE_LINE_SIZE 16
# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0x1000
# define HAL_DCACHE_LINE_SIZE 16
# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 32
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x10
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM966E)
# define HAL_ICACHE_SIZE 0
# define HAL_ICACHE_LINE_SIZE 0
# define HAL_ICACHE_WAYS 0
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
# define HAL_DCACHE_SIZE 0
# define HAL_DCACHE_LINE_SIZE 0
# define HAL_DCACHE_WAYS 0
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 32
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0
#else
# error "No cache details defined"
#endif
// FIXME: much of the code below should make better use of
// the definitions from hal_mmu.h
//-----------------------------------------------------------------------------
// Global control of Instruction cache
#if HAL_ICACHE_SIZE != 0
// FIXME: disable/enable instruction streaming?
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() \
CYG_MACRO_START \
asm volatile ( \
"mrc p15,0,r1,c1,c0,0;" \
"orr r1,r1,#0x1000;" \
"orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
/* that MMU and alignment faults */ \
/* are enabled) */ \
"mcr p15,0,r1,c1,c0,0" \
: \
: \
: "r1" /* Clobber list */ \
); \
CYG_MACRO_END
// Disable the instruction cache (and invalidate it, required semanitcs)
#define HAL_ICACHE_DISABLE() \
CYG_MACRO_START \
asm volatile ( \
"mrc p15,0,r1,c1,c0,0;" \
"bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
"mcr p15,0,r1,c1,c0,0;" \
"mov r1,#0;" \
"mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
"nop;" /* next few instructions may be via cache */ \
"nop;" \
"nop;" \
"nop;" \
"nop;" \
"nop" \
: \
: \
: "r1" /* Clobber list */ \
); \
CYG_MACRO_END
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
register cyg_uint32 reg; \
asm volatile ("mrc p15,0,%0,c1,c0,0" \
: "=r"(reg) \
: \
); \
(_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
CYG_MACRO_END
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
/* this macro can discard dirty cache lines (N/A for ICache) */ \
asm volatile ( \
"mov r1,#0;" \
"mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
"mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
"nop;" /* next few instructions may be via cache */ \
"nop;" \
"nop;" \
"nop;" \
"nop;" \
"nop;" \
: \
: \
: "r1" /* Clobber list */ \
); \
CYG_MACRO_END
// Synchronize the contents of the cache with memory.
// (which includes flushing out pending writes)
#define HAL_ICACHE_SYNC() \
CYG_MACRO_START \
HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
CYG_MACRO_END
#else
#define HAL_ICACHE_ENABLE()
#define HAL_ICACHE_DISABLE()
#define HAL_ICACHE_IS_ENABLED(_state_) ((_state_) = 0)
#define HAL_ICACHE_INVALIDATE_ALL()
#define HAL_ICACHE_SYNC()
#endif
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
// Unlock entire cache
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