📄 aaed2000_misc.c
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//==========================================================================
//
// aaed2000_misc.c
//
// HAL misc board support code for ARM9/AAED2000
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: hmt, Travis C. Furrer <furrer@mit.edu>, jskov
// Date: 2000-05-21
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/aaed2000.h> // Platform specifics
#include <cyg/infra/diag.h> // diag_printf
#include <string.h> // memset
// -------------------------------------------------------------------------
// MMU initialization:
//
// These structures are laid down in memory to define the translation
// table.
//
/*
* ARM Translation Table Base Bit Masks */
#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
/*
* ARM Domain Access Control Bit Masks
*/
#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
struct ARM_MMU_FIRST_LEVEL_FAULT {
int id : 2;
int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
int id : 2;
int imp : 2;
int domain : 4;
int sbz : 1;
int base_address : 23;
};
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
struct ARM_MMU_FIRST_LEVEL_SECTION {
int id : 2;
int b : 1;
int c : 1;
int imp : 1;
int domain : 4;
int sbz0 : 1;
int ap : 2;
int sbz1 : 8;
int base_address : 12;
};
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
struct ARM_MMU_FIRST_LEVEL_RESERVED {
int id : 2;
int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
(unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
cacheable, bufferable, perm) \
CYG_MACRO_START \
register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
\
desc.word = 0; \
desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
desc.section.imp = 1; \
desc.section.domain = 0; \
desc.section.c = (cacheable); \
desc.section.b = (bufferable); \
desc.section.ap = (perm); \
desc.section.base_address = (actual_base); \
*ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
= desc.word; \
CYG_MACRO_END
#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
{ int i; int j = abase; int k = vbase; \
for (i = size; i > 0 ; i--,j++,k++) \
{ \
ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
} \
}
union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
unsigned long word;
struct ARM_MMU_FIRST_LEVEL_FAULT fault;
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
struct ARM_MMU_FIRST_LEVEL_SECTION section;
struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
};
#define ARM_UNCACHEABLE 0
#define ARM_CACHEABLE 1
#define ARM_UNBUFFERABLE 0
#define ARM_BUFFERABLE 1
#define ARM_ACCESS_PERM_NONE_NONE 0
#define ARM_ACCESS_PERM_RO_NONE 0
#define ARM_ACCESS_PERM_RO_RO 0
#define ARM_ACCESS_PERM_RW_NONE 1
#define ARM_ACCESS_PERM_RW_RO 2
#define ARM_ACCESS_PERM_RW_RW 3
void
hal_mmu_init(void)
{
unsigned long ttb_base = AAED2000_SDRAM_PHYS_BASE + 0x4000;
unsigned long i;
/*
* Set the TTB register
*/
asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
/*
* Set the Domain Access Control Register
*/
i = ARM_ACCESS_TYPE_MANAGER(0) |
ARM_ACCESS_TYPE_NO_ACCESS(1) |
ARM_ACCESS_TYPE_NO_ACCESS(2) |
ARM_ACCESS_TYPE_NO_ACCESS(3) |
ARM_ACCESS_TYPE_NO_ACCESS(4) |
ARM_ACCESS_TYPE_NO_ACCESS(5) |
ARM_ACCESS_TYPE_NO_ACCESS(6) |
ARM_ACCESS_TYPE_NO_ACCESS(7) |
ARM_ACCESS_TYPE_NO_ACCESS(8) |
ARM_ACCESS_TYPE_NO_ACCESS(9) |
ARM_ACCESS_TYPE_NO_ACCESS(10) |
ARM_ACCESS_TYPE_NO_ACCESS(11) |
ARM_ACCESS_TYPE_NO_ACCESS(12) |
ARM_ACCESS_TYPE_NO_ACCESS(13) |
ARM_ACCESS_TYPE_NO_ACCESS(14) |
ARM_ACCESS_TYPE_NO_ACCESS(15);
asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
/*
* First clear all TT entries - ie Set them to Faulting
*/
memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
/* Actual Virtual Size Attributes Function */
/* Base Base MB cached? buffered? access permissions */
/* xxx00000 xxx00000 */
X_ARM_MMU_SECTION(0x000, 0x600, 32, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace CS0 */
X_ARM_MMU_SECTION(0x100, 0x100, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Ethernet */
X_ARM_MMU_SECTION(0x300, 0x300, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* AAED2000 board registers */
X_ARM_MMU_SECTION(0x400, 0x400, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA slot - I/O */
X_ARM_MMU_SECTION(0x440, 0x440, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA slot - stat*/
X_ARM_MMU_SECTION(0x480, 0x480, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA slot - attribute */
X_ARM_MMU_SECTION(0x4C0, 0x4C0, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA slot - common */
X_ARM_MMU_SECTION(0x500, 0x500, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CF slot - I/O */
X_ARM_MMU_SECTION(0x540, 0x540, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CF slot - stat*/
X_ARM_MMU_SECTION(0x580, 0x580, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CF slot - attribute */
X_ARM_MMU_SECTION(0x5C0, 0x5C0, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CF slot - common */
X_ARM_MMU_SECTION(0x800, 0x800, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* AAEC2000 registers */
// DRAM is non-contiguous, laid out in weird and wonderful ways...
X_ARM_MMU_SECTION(0xF00, 0x000, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xF10, 0x004, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xF40, 0x008, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xF50, 0x00C, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xF80, 0x010, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xF90, 0x014, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xFC0, 0x018, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xFD0, 0x01C, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
// Map in DRAM raw as well
X_ARM_MMU_SECTION(0xF00, 0xF00, 256, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Raw SDRAM */
}
//
// Platform specific initialization
//
void
plf_hardware_init(void)
{
HAL_WRITE_UINT8(AAEC_PCDR, 0x22);
HAL_WRITE_UINT8(AAEC_PCCDR, 0);
HAL_WRITE_UINT8(AAEC_PBDDR, 0x83);
HAL_WRITE_UINT8(AAEC_PINMUX,
AAEC_PINMUX_UART3CON | AAEC_PINMUX_PD0CON | AAEC_PINMUX_PE0CON);
// FIXME - all platform interrupt sources should be configured here
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_TS, 0, 0 ); // Low pulse
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_ETH, 0, 1 ); // High pulse
}
//
// Support for platform specific I/O channels
//
externC void lcd_comm_init(void);
void
plf_if_init(void)
{
aaed2000_KeyboardInit();
#ifdef CYGSEM_AAED2000_LCD_COMM
// Initialize I/O channel
lcd_comm_init();
#endif
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