aaed2000.h

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#ifndef CYGONCE_AAED2000_H
#define CYGONCE_AAED2000_H
/*=============================================================================
//
//      aaed2000.h
//
//      Platform specific support (register layout, etc)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: gthomas, jskov
// Date:         2001-10-30
// Purpose:      Agilent/AAED2000 platform specific support routines
// Description: 
// Usage:        #include <cyg/hal/aaed2000.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

//---------------------------------------------------------------------------
// Memory layout details needed by conversion macro
#define AAED2000_SDRAM_PHYS_BASE         0xF0000000
#define AAED2000_SDRAM_VIRT_BASE         0x00000000
#define AAED2000_SDRAM_SIZE              0x02000000
#define AAED2000_SDRAM_MASK              (AAED2000_SDRAM_SIZE-1)

#define AAED2000_FLASH_PHYS_BASE         0x00000000
#define AAED2000_FLASH_VIRT_BASE         0x60000000
#define AAED2000_FLASH_SIZE              0x02000000
#define AAED2000_FLASH_MASK              (AAED2000_FLASH_SIZE-1)

//---------------------------------------------------------------------------
// Clock and state controller
#define AAEC_CSC_BLEOI            0x80000410 // battery low end of interrupt
#define AAEC_CSC_MCEOI            0x80000414 // media changed end of interrupt
#define AAEC_CSC_TEOI             0x80000418 // tick end of interrupt
#define AAEC_CSC_CLKSET           0x80000420

#define AAEC_CSC_CLKSET_PLL       0x80000000
#define AAEC_CSC_CLKSET_SMCROM    0x01000000
#define AAEC_CSC_CLKSET_PS(_n_)       ((_n_)<<18) // values 0-3
#define AAEC_CSC_CLKSET_PCLKDIV(_n_)  ((_n_)<<16) // values 0-3
#define AAEC_CSC_CLKSET_MAINDIV2(_n_) ((_n_)<<11) // values 0-31
#define AAEC_CSC_CLKSET_MAINDIV1(_n_) ((_n_)<<7)  // values 0-15
#define AAEC_CSC_CLKSET_PREDIV(_n_)   ((_n_)<<2)  // values 0-31
#define AAEC_CSC_CLKSET_HCLKDIV(_n_)  ((_n_))     // values 0-3


#define CYGNUM_HAL_ARM_AAED2000_BUS_CLOCK_MHZ ((CYGNUM_HAL_ARM_AAED2000_BUS_CLOCK+500000)/1000000)

#define AAEC_CSC_CLKSET_INIT                                            \
  (  AAEC_CSC_CLKSET_HCLKDIV(CYGNUM_HAL_ARM_AAED2000_CLOCK_HCLKDIV)     \
   | AAEC_CSC_CLKSET_PREDIV(CYGNUM_HAL_ARM_AAED2000_CLOCK_PREDIV)       \
   | AAEC_CSC_CLKSET_MAINDIV1(CYGNUM_HAL_ARM_AAED2000_CLOCK_MAINDIV1)   \
   | AAEC_CSC_CLKSET_MAINDIV2(CYGNUM_HAL_ARM_AAED2000_CLOCK_MAINDIV2)   \
   | AAEC_CSC_CLKSET_PCLKDIV(CYGNUM_HAL_ARM_AAED2000_CLOCK_PCLKDIV)     \
   | AAEC_CSC_CLKSET_PS(CYGNUM_HAL_ARM_AAED2000_CLOCK_PS)               \
   | AAEC_CSC_CLKSET_SMCROM)

//---------------------------------------------------------------------------
// Interrupt controller
#define AAEC_INT_SR               0x80000500
#define AAEC_INT_RSR              0x80000504  // Raw [unmasked] interrupt status
#define AAEC_INT_ENS              0x80000508
#define AAEC_INT_ENC              0x8000050c
#define AAEC_INT_TEST1            0x80000514
#define AAEC_INT_TEST2            0x80000518

#define AAEC_INTS_T3OI            CYGNUM_HAL_INTERRUPT_TC3OI // Timer #3 overflow

//---------------------------------------------------------------------------
// UARTs
#define AAEC_UART1                0x80000600
#define AAEC_UART2                0x80000700
#define AAEC_UART3                0x80000800

#define AAEC_UART2_UMS2EOI        0x80000714 // modem end of interrupt
#define AAEC_UART2_UMS3EOI        0x80000814 // modem end of interrupt

#define AAEC_UART_DATA    0x0000  // Data/FIFO register
#define AAEC_UART_LCR     0x0004  // Control register
#define AAEC_UART_LCR_BRK      0x0001 // Send break
#define AAEC_UART_LCR_PEN      0x0002 // Enable parity
#define AAEC_UART_LCR_EP       0x0004 // Odd/Even parity
#define AAEC_UART_LCR_S2       0x0008 // One/Two stop bits
#define AAEC_UART_LCR_FIFO     0x0010 // Enable FIFO
#define AAEC_UART_LCR_WL5      0x0000 // Word length - 5 bits
#define AAEC_UART_LCR_WL6      0x0020 // Word length - 6 bits
#define AAEC_UART_LCR_WL7      0x0040 // Word length - 7 bits
#define AAEC_UART_LCR_WL8      0x0060 // Word length - 8 bits
#define AAEC_UART_BAUD    0x0008  // Baud rate
#define AAEC_UART_CTRL    0x000C  // Control register
#define AAEC_UART_CTRL_ENAB    0x0001 // Enable uart
#define AAEC_UART_CTRL_SIR     0x0002 // Enable SIR IrDA
#define AAEC_UART_CTRL_SIRLP   0x0004 // Enable low power IrDA
#define AAEC_UART_CTRL_RXP     0x0008 // Receive pin polarity
#define AAEC_UART_CTRL_TXP     0x0010 // Transmit pin polarity
#define AAEC_UART_CTRL_MXP     0x0020 // Modem pin polarity
#define AAEC_UART_CTRL_LOOP    0x0040 // Loopback mode
#define AAEC_UART_CTRL_SIRBD   0x0080 // blanking disable
#define AAEC_UART_STATUS  0x0010  // Status
#define AAEC_UART_STATUS_CTS   0x0001 // Clear-to-send status
#define AAEC_UART_STATUS_DSR   0x0002 // Data-set-ready status
#define AAEC_UART_STATUS_DCD   0x0004 // Data-carrier-detect status
#define AAEC_UART_STATUS_TxBSY 0x0008 // Transmitter busy
#define AAEC_UART_STATUS_RxFE  0x0010 // Receive FIFO empty
#define AAEC_UART_STATUS_TxFF  0x0020 // Transmit FIFO full
#define AAEC_UART_STATUS_RxFF  0x0040 // Receive FIFO full
#define AAEC_UART_STATUS_TxFE  0x0080 // Transmit FIFO empty
#define AAEC_UART_INT     0x0014  // Interrupt status
#define AAEC_UART_INTM    0x0018  // Interrupt mask register
#define AAEC_UART_INTRES  0x001c  // Interrupt result (masked interrupt status)
#define AAEC_UART_INT_RIS      0x0001 // Rx interrupt
#define AAEC_UART_INT_TIS      0x0002 // Tx interrupt
#define AAEC_UART_INT_MIS      0x0004 // Modem status interrupt
#define AAEC_UART_INT_RTIS     0x0008 // Rx timeout interrupt
//#define AAEC_UART_MCTRL   0x0100  // Modem control

//---------------------------------------------------------------------------
// Pump control
#define AAEC_PUMP_CONTROL         0x80000900   // Control
#define AAEC_PUMP_FREQUENCY       0x80000908   // Frequency

//---------------------------------------------------------------------------
// Codec
#define AAEC_COD_CDEOI            0x80000a0c // codec end of interrupt

//---------------------------------------------------------------------------
// Synchronous Serial Peripheral (SSP)
#define AAEC_SSP_CR0              0x80000B00   // Control Register 0
#define AAEC_SSP_CR0_SCR            8            // Serial clock rate - Bits 15..8
#define AAEC_SSP_CR0_SCR_MASK       (0x7F<<AAEC_SSP_CR0_SCR)    
#define AAEC_SSP_CR0_SSE            7            // SSP enable/disable
#define AAEC_SSP_CR0_SSE_MASK       (1<<AAEC_SSP_CR0_SSE)
#define AAEC_SSP_CR0_SSE_ON         1
#define AAEC_SSP_CR0_SSE_OFF        0
#define AAEC_SSP_CR0_FRF            4            // Frame format
#define AAEC_SSP_CR0_FRF_MASK       (0x3<<AAEC_SSP_CR0_FRF)
#define AAEC_SSP_CR0_FRF_MOT        0               // Motorola SPI
#define AAEC_SSP_CR0_FRF_TI         1               // TI synchronous serial frame
#define AAEC_SSP_CR0_FRF_NAT        2               // National microwire
#define AAEC_SSP_CR0_SIZE           0            // Data size
#define AAEC_SSP_CR0_SIZE_MASK      (0xF<<AAEC_SSP_CR0_SIZE)
#define AAEC_SSP_CR1              0x80000B04   // Control Register 1
#define AAEC_SSP_CR1_TXIDLE         7            // Tx idle interrupt
#define AAEC_SSP_CR1_FEN            6            // FIFO enable
#define AAEC_SSP_CR1_RORIE          5            // Rx FIFO overrun interrupt
#define AAEC_SSP_CR1_SPH            4            // SCLK phase
#define AAEC_SSP_CR1_SPO            3            // SCLK polarity
#define AAEC_SSP_CR1_LBM            2            // Lookpback
#define AAEC_SSP_CR1_TIE            1            // Tx interrupt
#define AAEC_SSP_CR1_RIE            0            // Rx Interrupt
#define AAEC_SSP_IIR              0x80000B08   // Interrupt ID register (read)
#define AAEC_SSP_IIR_TXIDLE         7            // Tx idle interrupt