innovator.h

开放源码实时操作系统源码.

#ifndef CYGONCE_INNOVATOR_H
#define CYGONCE_INNOVATOR_H

//=============================================================================
//
//      innovator.h
//
//      Platform specific support (register layout, etc)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Patrick Doyle <[e-mail]>
// Contributors: Patrick Doyle <[e-mail]>
// Date:         2002-12-01
// Purpose:      Innovator platform specific support definitions
// Description: 
// Usage:        #include <cyg/hal/innovator.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal_arm_arm9_innovator.h>

// Memory mapping
#define FLASH_CS0_BASE     0x00000000
#define FLASH_CS1_BASE     0x04000000
#define FLASH_CS2_BASE     0x08000000
#define FLASH_CS3_BASE     0x0C000000
#define SDRAM_BASE         0x10000000
#define INTERNAL_SRAM_BASE 0x20000000

// Most of this should be moved to a separate omap.h or omap_1510.h file
// CLKM Registers
#define CLKM_BASE         0xFFFECE00
#define _CLKM_ARM_CKCTL   0x00
#define _CLKM_ARM_IDLECT1 0x04
#define _CLKM_ARM_IDLECT2 0x08
#define _CLKM_ARM_EWUPCT  0x0C
#define _CLKM_ARM_RSTCT1  0x10
#define _CLKM_ARM_RSTCT2  0x14
#define _CLKM_ARM_SYSST   0x18

#define CLKM_ARM_CKCTL   (volatile short *)(CLKM_BASE + _CLKM_ARM_CKCTL)
#define CLKM_ARM_IDLECT1 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT1)
#define CLKM_ARM_IDLECT2 (volatile short *)(CLKM_BASE + _CLKM_ARM_IDLECT2)
#define CLKM_ARM_EWUPCT  (volatile short *)(CLKM_BASE + _CLKM_ARM_EWUPCT)
#define CLKM_ARM_RSTCT1  (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT1)
#define CLKM_ARM_RSTCT2  (volatile short *)(CLKM_BASE + _CLKM_ARM_RSTCT2)
#define CLKM_ARM_SYSST   (volatile short *)(CLKM_BASE + _CLKM_ARM_SYSST)

// Watchdog Registers
#define WATCHDOG_BASE 0xFFFEC800
#define _WD_CNTL_TIMER 0x00
#define _WD_LOAD_TIM   0x04
#define _WD_READ_TIM   0x04
#define _WD_TIMER_MODE 0x08

#define WATCHDOG_CNTL_TIMER (volatile short *)(WATCHDOG_BASE + _WD_CNTL_TIMER)
#define WATCHDOG_LOAD_TIM   (volatile short *)(WATCHDOG_BASE + _WD_LOAD_TIM)
#define WATCHDOG_READ_TIM   (volatile short *)(WATCHDOG_BASE + _WD_READ_TIM)
#define WATCHDOG_TIMER_MODE (volatile short *)(WATCHDOG_BASE + _WD_TIMER_MODE)

/* Nothing below this line has been scrubbed yet */
/* DPLL Registers */
#define DPLL1_BASE    0xFFFECF00
#define DPLL2_BASE    0xFFFED000
#define DPLL3_BASE    0xFFFED100

#define _DPLL_CTL_REG 0x00

#define DPLL1_CTL_REG (volatile short *)(DPLL1_BASE + _DPLL_CTL_REG)
#define DPLL2_CTL_REG (volatile short *)(DPLL2_BASE + _DPLL_CTL_REG)
#define DPLL3_CTL_REG (volatile short *)(DPLL3_BASE + _DPLL_CTL_REG)

#define FPGA_BASE     0x08000000    /* CS2_BASE */
#define CONFIG_BASE   0xFFFE1000
#define TC_BASE       0xFFFECC00

/* FPGA Registers */
#define FPGA_PWR_CTRL_REG      (*(volatile char     *)(FPGA_BASE     + 0x05))

/* Configuration Registers */
#define CONFIG_FUNC_MUX_CTRL_0 (*(volatile unsigned *)(CONFIG_BASE   + 0x00))
#define CONFIG_FUNC_MUX_CTRL_1 (*(volatile unsigned *)(CONFIG_BASE   + 0x04))
#define CONFIG_FUNC_MUX_CTRL_2 (*(volatile unsigned *)(CONFIG_BASE   + 0x08))

/* Traffic Controller Registers */
#define TC_IMIF_PRIO           (*(volatile unsigned *)(TC_BASE       + 0x00))
#define TC_EMIFS_PRIO_REG      (*(volatile unsigned *)(TC_BASE       + 0x04))
#define TC_EMIFF_PRIO_REG      (*(volatile unsigned *)(TC_BASE       + 0x08))
#define TC_EMIFS_CONFIG_REG    (*(volatile unsigned *)(TC_BASE       + 0x0C))
#define TC_EMIFS_CS0_CONFIG    (*(volatile unsigned *)(TC_BASE       + 0x10))
#define TC_EMIFS_CS1_CONFIG    (*(volatile unsigned *)(TC_BASE       + 0x14))
#define TC_EMIFS_CS2_CONFIG    (*(volatile unsigned *)(TC_BASE       + 0x18))
#define TC_EMIFS_CS3_CONFIG    (*(volatile unsigned *)(TC_BASE       + 0x1C))
#define TC_EMIFF_SDRAM_CONFIG  (*(volatile unsigned *)(TC_BASE       + 0x20))
#define TC_EMIFF_MRS           (*(volatile unsigned *)(TC_BASE       + 0x24))
#define TC_TIMEOUT1            (*(volatile unsigned *)(TC_BASE       + 0x28))
#define TC_TIMEOUT2            (*(volatile unsigned *)(TC_BASE       + 0x2C))
#define TC_TIMEOUT3            (*(volatile unsigned *)(TC_BASE       + 0x30))
#define TC_ENDIANISM           (*(volatile unsigned *)(TC_BASE       + 0x34))

/* Believe it or not, these actually make the code more readable in a few
 * places.
 */
#ifndef BIT_00
#define BIT_00 0x00000001
#define BIT_01 0x00000002
#define BIT_02 0x00000004
#define BIT_03 0x00000008
#define BIT_04 0x00000010
#define BIT_05 0x00000020
#define BIT_06 0x00000040
#define BIT_07 0x00000080
#define BIT_08 0x00000100
#define BIT_09 0x00000200
#define BIT_10 0x00000400
#define BIT_11 0x00000800
#define BIT_12 0x00001000
#define BIT_13 0x00002000
#define BIT_14 0x00004000
#define BIT_15 0x00008000
#define BIT_16 0x00010000
#define BIT_17 0x00020000
#define BIT_18 0x00040000
#define BIT_19 0x00080000
#define BIT_20 0x00100000
#define BIT_21 0x00200000
#define BIT_22 0x00400000
#define BIT_23 0x00800000
#define BIT_24 0x01000000
#define BIT_25 0x02000000
#define BIT_26 0x04000000
#define BIT_27 0x08000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
#endif

// We are using this
#define INNOVATOR_FLASH_VIRT_BASE 0x10000000
//  #define INNOVATOR_FLASH_PHYS_BASE 0x00000000
#define INNOVATOR_SDRAM_PHYS_BASE 0x10000000

#if 0
#define INNOVATOR_BASE         INNOVATOR_REGS_PHYS_BASE

//-----------------------------------------------------------------------------
// Boot control
// Note: this register is actually write-bit-to-clear-it
#define INNOVATOR_BOOT_CR      (INNOVATOR_BASE + 0x0000)

#define INNOVATOR_BOOT_CR_BM   0x00000001
#define INNOVATOR_BOOT_CR_HM   0x00000002
#define INNOVATOR_BOOT_CR_RE   0x00000004

//-----------------------------------------------------------------------------
// DPSRAM config
#define INNOVATOR_DPSRAM_BASE  (INNOVATOR_BASE + 0x0030)
#define _DPSRAM0_SR            0x0000
#define _DPSRAM0_LCR           0x0004
#define _DPSRAM1_SR            0x0008
#define _DPSRAM1_LCR           0x000c

#define _DPSRAM0_LCR_INIT      0x00000000
#define _DPSRAM1_LCR_INIT      0x00000000

//-----------------------------------------------------------------------------
// IO controller
#define INNOVATOR_IOCR_BASE    (INNOVATOR_BASE + 0x0040)
#define _IOCR_SDRAM            0x0000
#define _IOCR_EBI              0x0004
#define _IOCR_UART             0x0008
#define _IOCR_TRACE            0x000c

#define _IOCR_OC_PCI           0x00000008
#define _IOCR_OC_FAST          0x00000004
#define _IOCR_OC_SLOW          0x00000000
#define _IOCR_IO_STRIPE        0x00000002
#define _IOCR_LOCK             0x00000001

#define INNOVATOR_IOCR_SDRAM_INIT (_IOCR_OC_FAST | _IOCR_IO_STRIPE | _IOCR_LOCK)
#define INNOVATOR_IOCR_EBI_INIT   (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK)
#define INNOVATOR_IOCR_UART_INIT  (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK)


//-----------------------------------------------------------------------------
// Memory mapping
#define INNOVATOR_MMAP_BASE    (INNOVATOR_BASE + 0x0080)
#define _MMAP_REGISTERS        0x0000
#define _MMAP_SRAM0            0x0010
#define _MMAP_SRAM1            0x0014
#define _MMAP_DPSRAM0          0x0020
#define _MMAP_DPSRAM1          0x0024
#define _MMAP_SDRAM0           0x0030
#define _MMAP_SDRAM1           0x0034
#define _MMAP_EBI0             0x0040
#define _MMAP_EBI1             0x0044
#define _MMAP_EBI2             0x0048
#define _MMAP_EBI3             0x004c
#define _MMAP_PLD0             0x0050
#define _MMAP_PLD1             0x0054
#define _MMAP_PLD2             0x0058
#define _MMAP_PLD3             0x005c

#define _MMAP_SIZE_16K   (13<<7)
#define _MMAP_SIZE_64K   (15<<7)
#define _MMAP_SIZE_128K  (16<<7)
#define _MMAP_SIZE_1M    (19<<7)
#define _MMAP_SIZE_4M    (21<<7)