📄 hal_platform_setup.h
字号:
mov r0, #0x1800
again12:
subs r0, r0, #0x1
bne again12
FAKE_LED_MACRO(21)
// Misc 2
// ------
mov r1, #0xfb
ldr r0, REG_LB_CLOCK_DIV
str r1, [r0]
// *revisit-skranz* is needed?
mov r0, #0x1800
again4:
subs r0, r0, #0x1
bne again4
FAKE_LED_MACRO(22)
// ARM Clock Module Setup
// ----------------------
mov r1, #0x40
ldr r0, REG_ARM_IDLECT2
strh r1, [r0] // CLKM, Clock domain control.
mov r1, #0x01 // PER_EN bit
ldr r0, REG_ARM_RSTCT2
strh r1, [r0] // CLKM; Peripheral reset.
// Reset CLKM
#ifdef ORIGINAL_CODE
mov r1, #0x06 // Needed for UART[12]
#else
mov r1, #0x86 // Needed for UART[12]
#endif
ldr r0, REG_ARM_IDLECT2
strh r1, [r0] // CLKM, Clock domain control.
// Set CLKM to Sync-Scalable
mov r1, #0x1000 // Needed for UART[12]
ldr r0, REG_ARM_SYSST
strh r1, [r0]
// *revisit-skranz* is needed?
mov r0, #0x1800
again6:
subs r0, r0, #0x1
bne again6
FAKE_LED_MACRO(23)
ldr r1, VAL_ARM_CKCTL
ldr r0, REG_ARM_CKCTL
strh r1, [r0]
// setup DPLL1 Control Register
// ----------------------------
ldr r1, VAL_DPLL1_CTL
ldr r0, REG_DPLL1_CTL
strh r1, [r0]
ands r1, r1, #0x10 // Check if PLL is enabled.
beq finish2 // Do not look for lock if BYPASS selected
poll2:
ldrh r1, [r0]
ands r1, r1, #0x01 // Check the LOCK bit.
beq poll2 // ...loop until bit goes hi.
finish2:
FAKE_LED_MACRO(24)
// Setup TC EMIFS configuration.
// CS0 value based on 168MHz
// ---------------------------------------------------
ldr r1, VAL_TC_EMIFS_CS0_CONFIG // increase flash speed.
ldr r0, REG_TC_EMIFS_CS0_CONFIG
str r1, [r0] // Chip Select 0
ldr r1, VAL_TC_EMIFS_CS1_CONFIG
ldr r0, REG_TC_EMIFS_CS1_CONFIG
str r1, [r0] // Chip Select 1
ldr r1, VAL_TC_EMIFS_CS2_CONFIG
ldr r0, REG_TC_EMIFS_CS2_CONFIG
str r1, [r0] // Chip Select 2
ldr r1, VAL_TC_EMIFS_CS3_CONFIG
ldr r0, REG_TC_EMIFS_CS3_CONFIG
str r1, [r0] // Chip Select 3
// *revisit-skranz* is needed?
mov r0, #0x1800
again9:
subs r0, r0, #0x1
bne again9
FAKE_LED_MACRO(25)
// The following was added by WPD
// Set up a stack [for calling C code]
#ifdef CYG_HAL_STARTUP_ROM
// The startup stack is in internal SRAM
ldr sp,=__startup_stack
// This _MOST_DEFINATELY_ needs to be fixed
orr sp,sp,#0x10000000
#else
// The startup stack is in SDRAM, at some virtual address, but
// we have not set up the MMU yet, so we need to initialize SP
// with the physical address of '__startup_stack'
#error "Somehow"
#endif
bl hal_mmu_init
FAKE_LED_MACRO(26)
// Enable MMU
ldr r2,=10f
ldr r1,=MMU_Control_Init|MMU_Control_M
mcr MMU_CP,0,r1,MMU_Control,c0
mov pc,r2
// mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache
// mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs
10:
nop
nop
nop
FAKE_LED_MACRO(27)
#if 0
ldr r3,=0x20000000
str r1,[r3]
mrc MMU_CP,0,r1,MMU_Control,c0
str r1,[r3, #0x04]
mrc p15,0,r1,c15,c1,0
str r1,[r3, #0x08]
here:
// b here
#endif
#endif
.endm
#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_REDBOOT)
#define PLATFORM_SETUP1
#endif
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// end of hal_platform_setup.h
// ------------------------------------------------------
// --------------Static Data Definitions-----------------
// ------------------------------------------------------
/* inernal OMAP registers */
/* interrupt handler level 2 registers */
REG_IHL2_MIR: /* 32 bits */
.word 0xfffe0004
/* OMAP configuration registers */
REG_FUNC_MUX_CTRL_0: /* 32 bits */
.word 0xfffe1000
REG_FUNC_MUX_CTRL_1: /* 32 bits */
.word 0xfffe1004
REG_FUNC_MUX_CTRL_2: /* 32 bits */
.word 0xfffe1008
REG_COMP_MODE_CTRL_0: /* 32 bits */
.word 0xfffe100c
REG_FUNC_MUX_CTRL_3: /* 32 bits */
.word 0xfffe1010
REG_FUNC_MUX_CTRL_4: /* 32 bits */
.word 0xfffe1014
REG_FUNC_MUX_CTRL_5: /* 32 bits */
.word 0xfffe1018
REG_FUNC_MUX_CTRL_6: /* 32 bits */
.word 0xfffe101c
REG_FUNC_MUX_CTRL_7: /* 32 bits */
.word 0xfffe1020
REG_FUNC_MUX_CTRL_8: /* 32 bits */
.word 0xfffe1024
REG_FUNC_MUX_CTRL_9: /* 32 bits */
.word 0xfffe1028
REG_FUNC_MUX_CTRL_A: /* 32 bits */
.word 0xfffe102C
REG_FUNC_MUX_CTRL_B: /* 32 bits */
.word 0xfffe1030
REG_FUNC_MUX_CTRL_C: /* 32 bits */
.word 0xfffe1034
REG_FUNC_MUX_CTRL_D: /* 32 bits */
.word 0xfffe1038
REG_PULL_DWN_CTRL_0: /* 32 bits */
.word 0xfffe1040
REG_PULL_DWN_CTRL_1: /* 32 bits */
.word 0xfffe1044
REG_PULL_DWN_CTRL_2: /* 32 bits */
.word 0xfffe1048
REG_PULL_DWN_CTRL_3: /* 32 bits */
.word 0xfffe104c
REG_VOLTAGE_CTRL_0: /* 32 bits */
.word 0xfffe1060
REG_TEST_DBG_CTRL_0: /* 32 bits */
.word 0xfffe1070
REG_MOD_CONF_CTRL_0: /* 32 bits */
.word 0xfffe1080
/* local bus control registers */
REG_LB_CLOCK_DIV: /* 32 bits */
.word 0xfffec10c
/* watchdog timer registers */
REG_WDT_TIMER_MODE: /* 16 bits */
.word 0xfffec808
/* interrupt handler level 1 registers */
REG_IHL1_MIR: /* 32 bits */
.word 0xfffecb04
/* traffic controller memory interface registers */
REG_TC_IMIF_PRIO: /* 32 bits */
.word 0xfffecc00
REG_TC_EMIFS_PRIO: /* 32 bits */
.word 0xfffecc04
REG_TC_EMIFF_PRIO: /* 32 bits */
.word 0xfffecc08
REG_TC_EMIFS_CONFIG: /* 32 bits */
.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
.word 0xfffecc1c
REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
.word 0xfffecc20
REG_TC_EMIFF_MRS: /* 32 bits */
.word 0xfffecc24
/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL: /* 16 bits */
.word 0xfffece00
REG_ARM_IDLECT2: /* 16 bits */
.word 0xfffece08
REG_ARM_RSTCT2: /* 16 bits */
.word 0xfffece14
REG_ARM_SYSST: /* 16 bits */
.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL: /* 16 bits */
.word 0xfffecf00
/* identification code register */
REG_IDCODE: /* 32 bits */
.word 0xfffed404
/* board-specific registers */
REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
.word 0x08000003
REG_FPGA_POWER: /* 8 bits */
.word 0x08000005
REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
.word 0x0800000c
REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
.word 0x0800000e
/* constants */
VAL_COMP_MODE_CTRL_0:
.word 0x0000eaef
VAL_FUNC_MUX_CTRL_4:
.word 0x00000000
VAL_FUNC_MUX_CTRL_5:
.word 0x00000000
VAL_FUNC_MUX_CTRL_6:
.word 0x00000001
VAL_FUNC_MUX_CTRL_7:
.word 0x00000000
VAL_FUNC_MUX_CTRL_8:
.word 0x10001200
VAL_FUNC_MUX_CTRL_9:
.word 0x01201012
VAL_FUNC_MUX_CTRL_A:
.word 0x00000248
VAL_FUNC_MUX_CTRL_B:
.word 0x00000248
VAL_FUNC_MUX_CTRL_C:
.word 0x09000000
VAL_FUNC_MUX_CTRL_D:
.word 0x00000000
VAL_PULL_DWN_CTRL_0:
.word 0x11a10000
VAL_PULL_DWN_CTRL_1:
.word 0x2e047fff
VAL_PULL_DWN_CTRL_2:
.word 0xffd7d3e6
VAL_PULL_DWN_CTRL_3:
.word 0x00003f03
VAL_VOLTAGE_CTRL_0:
.word 0x00000007
VAL_TEST_DBG_CTRL_0:
/* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
* says to write a 7. Don't know what the right thing is to do, so
* I'm leaving it at 7 since that's what was already here.
*/
.word 0x00000007
VAL_MOD_CONF_CTRL_0:
.word 0x0b000008
VAL_ARM_CKCTL:
#ifdef ORIGINAL_CODE
.word 0x110f
#else
.word 0x010f
#endif
VAL_DPLL1_CTL:
.word 0x2710
VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
.word 0x00001149
VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
.word 0x00004158
VAL_TC_EMIFS_CS0_CONFIG:
.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
.word 0x0000f559
VAL_TC_EMIFS_CS2_CONFIG:
.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
.word 0x00003331
VAL_TC_EMIFF_SDRAM_CONFIG:
.word 0x010290fc
VAL_TC_EMIFF_MRS:
.word 0x00000027
V_0xffffffff:
.word 0xffffffff
V_0x0000ff22:
.word 0x0000ff22
#endif // CYGONCE_HAL_PLATFORM_SETUP_H
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