hal_platform_setup.h

开放源码实时操作系统源码.

        ldr     r2,=10f
       	ldr	r1,=MMU_Control_Init|MMU_Control_M
        mcr	MMU_CP,0,r1,MMU_Control,c0
        mov     pc,r2

        //        mcr     MMU_CP,0,r0,MMU_InvalidateCache,c7,0	// Flush data and instruction cache
        //	mcr     MMU_CP,0,r0,MMU_TLB,c7,0        	// Flush ID TLBs
10:     
        nop
        nop
        nop

#if 0
        ldr     r3,=0x20000000
        str     r1,[r3]
        mrc     MMU_CP,0,r1,MMU_Control,c0
        str     r1,[r3, #0x04]
        mrc     p15,0,r1,c15,c1,0
        str     r1,[r3, #0x08]

here:
        //        b       here
#endif
#else   // PLATFORM_SETUP_FROM_CCS_GEL_SCRIPT
	// This is all stolen from the ipaq setup

        // Make sure MMU is OFF
	mov r0,#INTERNAL_SRAM_BASE // Force cache writeback by reloading
	add r2,r0,#0x2000	   // cache from the internal memory bank
123:    ldr r1,[r0],#16
	cmp r0, r2
	bne 123b
	mov r0,#0
	mov r1,#0x0070		// MMU Control System bit
	mcr p15,0,r0,c7,c7,0	// Flush data and instruction cache
	mcr p15,0,r0,c8,c7,0	// Flush ID TLBs
	mcr p15,0,r0,c9,c0,0	// Flush Read-Buffer
	mcr p15,0,r0,c7,c10,4	// Drain write buffer
	mcr p15,0,r0,c13,c0,0	// Disable virtual ID mapping
	mcr p15,0,r1,c1,c0,0	// Write MMU control register
	nop; nop; nop; nop
        FAKE_LED_MACRO(2)

        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0
        FAKE_LED_MACRO(3)

        // This is the platform setup adapted from the rrload setup implied
        // by head_omap1510.S

// Disable the Watchdog Timer.
// ---------------------------
        mov  r1, #0xF5
        ldr  r0, REG_WDT_TIMER_MODE
        strh r1, [r0]  // Set WDTIM Mode
        mov  r1, #0xA0
        strh r1, [r0]  // Set WDTIM Mode
        FAKE_LED_MACRO(4)

// setting for DPLL1 control register.
// ----------------------------------
        ldr  r0, REG_DPLL1_CTL
        mov  r1, #0x10
        strh r1, [r0]
// Continue to loop if bit shows "not locked"
poll1:
        ldrh r1, [r0]
        ands r1, r1, #0x01
        beq  poll1
        FAKE_LED_MACRO(5)

// Init Arm9 processor.
// --------------------
        mrs r0, cpsr            // Get current mode bits.
        bic r0, r0, #0x1f        // Clear mode bits.
        orr r0, r0, #0xd3        // Disable IRQs/FIQs, supervisor mode.
        msr cpsr, r0            // Enter Supervisor mode.
        mov r1, #0x81           // Set ARM925T configuration.
        mcr p15, 0, r1, c15, c1, 0  // Write ARM925T configuration register.
        FAKE_LED_MACRO(6)

// Disable All Interrupts
// -----------
        ldr r1, V_0xffffffff
        ldr r0, REG_IHL1_MIR
        str r1, [r0]
        ldr r0, REG_IHL2_MIR
        str r1, [r0]
        FAKE_LED_MACRO(7)

// Determine if this is a 1509 or 1510, then
// set the Configuration Registers accordingly
// 1509 shows 0, 1510 shows 0x1b47002f
// -------------------
        ldr     r0, REG_IDCODE
        ldr     r1, [r0]
        cmp     r1, #0x0
        beq     omap1509
        FAKE_LED_MACRO(8)
        
// OK, so we're a 1510.  
omap1510:
/*
        Errata for ES1 says to do this:

        1)  Check for power-on or warm reset.
        2)  Configure SDRAM controller depending on reset type.
*/
        // Check for reset type
        ldr     r0, REG_ARM_SYSST
        ldrh    r1, [r0]
        mov     r2, #0x20
        tst     r2, r1
        beq     zzz_warm_reset
        FAKE_LED_MACRO(9)

POR:
        // Wait 100mS for SDRAM to stabilize before
        // configuring SDRAM controller.
        // Number guessed at.
        mov     r0, #0x2000
1:      subs    r0, r0, #0x1
        bne     1b
        FAKE_LED_MACRO(10)
        
        b       after_initial_configure_SDRAM
        
zzz_warm_reset:
        FAKE_LED_MACRO(11)
      
        // Set auto-refresh counter value to 1.
        // Program MRS to appropriate CAS latency
        // Wait for SDRAM array to be completely
        // refreshed, 1 cycle * #SDRAM rows.
        ldr     r0, REG_TC_EMIFF_SDRAM_CONFIG
        mov     r1, #0x100
        str     r1, [r0]
        ldr     r0, REG_TC_EMIFF_MRS
        ldr     r1, VAL_TC_EMIFF_MRS
        str     r1, [r0]
        mov     r2, #0x2000
1:      subs    r2, r2, #0x1
        bne     1b
        ldr     r0, REG_TC_EMIFF_SDRAM_CONFIG
        mov     r1, #0x10000
        str     r1, [r0]     
                
after_initial_configure_SDRAM:        
        FAKE_LED_MACRO(12)
                        

// Config Spec says to write values
// to each of the configuration registers,
// then take the chip out of 1509 compatibility mode.

        ldr     r0, REG_PULL_DWN_CTRL_0
        ldr     r1, VAL_PULL_DWN_CTRL_0
        str     r1, [r0]
        ldr     r0, REG_PULL_DWN_CTRL_1
        ldr     r1, VAL_PULL_DWN_CTRL_1
        str     r1, [r0]
        ldr     r0, REG_PULL_DWN_CTRL_2
        ldr     r1, VAL_PULL_DWN_CTRL_2
        str     r1, [r0]
        ldr     r0, REG_PULL_DWN_CTRL_3
        ldr     r1, VAL_PULL_DWN_CTRL_3
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_4
        ldr     r1, VAL_FUNC_MUX_CTRL_4
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_5
        ldr     r1, VAL_FUNC_MUX_CTRL_5
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_6
        ldr     r1, VAL_FUNC_MUX_CTRL_6
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_7
        ldr     r1, VAL_FUNC_MUX_CTRL_7
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_8
        ldr     r1, VAL_FUNC_MUX_CTRL_8
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_9
        ldr     r1, VAL_FUNC_MUX_CTRL_9
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_A
        ldr     r1, VAL_FUNC_MUX_CTRL_A
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_B
        ldr     r1, VAL_FUNC_MUX_CTRL_B
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_C
        ldr     r1, VAL_FUNC_MUX_CTRL_C
        str     r1, [r0]
        ldr     r0, REG_FUNC_MUX_CTRL_D
        ldr     r1, VAL_FUNC_MUX_CTRL_D
        str     r1, [r0]
        ldr     r0, REG_VOLTAGE_CTRL_0
        ldr     r1, VAL_VOLTAGE_CTRL_0
        str     r1, [r0]
        ldr     r0, REG_TEST_DBG_CTRL_0
        ldr     r1, VAL_TEST_DBG_CTRL_0
        str     r1, [r0]
        ldr     r0, REG_MOD_CONF_CTRL_0
        ldr     r1, VAL_MOD_CONF_CTRL_0
        str     r1, [r0]
        FAKE_LED_MACRO(13)

        // Take out of compatibility mode
        ldr     r0, REG_COMP_MODE_CTRL_0
        ldr     r1, VAL_COMP_MODE_CTRL_0
        str     r1, [r0]
        FAKE_LED_MACRO(14)

        b post_config_registers
        
omap1509:       
        ldr     r0, REG_FUNC_MUX_CTRL_0
        ldr     r1, [r0]
        orr     r1, r1, #0x6000000  // UART_GIGA_GATE bit as well as UART_BT_GATE bit
        str     r1, [r0]
// Errata for ES5.5 says this must be done before DSP or MPU can
// access internal RAMs.  This is benign for earlier revs.
        ldr     r0, REG_FUNC_MUX_CTRL_1
        mov     r1, #0xc
        str     r1, [r0]
        
post_config_registers:          
        FAKE_LED_MACRO(15)
        mov r0, #0x1800
again:        
        subs r0, r0, #0x1
        bne again
        FAKE_LED_MACRO(16)

// Invalidate cache
// -----------------
        mov r0,#0
        nop
        mcr p15, 0x0, r0, c7, c5, 0x0  
        nop
        nop
        nop
        nop
        FAKE_LED_MACRO(17)

//  Enable I-Cache
// -------------
        mrc p15, 0x0, r1, c1, c0, 0x0
        orr r1, r1, #0x1000
        nop
        mcr p15, 0x0, r1, c1, c0, 0x0
        nop
        nop
        nop
        nop
        FAKE_LED_MACRO(18)

// Initialize Traffic Controller (TC)
// ----------------------------------
        ldr r0, REG_TC_IMIF_PRIO
        mov r1, #0x0
        str r1, [r0]
        ldr r0, REG_TC_EMIFS_PRIO
        str r1, [r0]
        ldr r0, REG_TC_EMIFF_PRIO
        str r1, [r0]
        
        ldr r0, REG_TC_EMIFS_CONFIG
        ldr r1, [r0]
        bic r1, r1, #0x08	/* clear the global power-down enable PDE bit */
        bic r1, r1, #0x01	/* write protect flash by clearing the WP bit */
        str r1, [r0]  // EMIFS GlB Configuration. (value 0x12 most likely)

// Set TC chip select registers
// SDRAM value based on 168MHz 1510.
// ----------------------------
        ldr r0, REG_TC_EMIFS_CS1_CONFIG
        ldr r1, VAL_TC_EMIFS_CS1_CONFIG_PRELIM
        str r1, [r0]
        ldr r0, REG_TC_EMIFS_CS2_CONFIG
        ldr r1, VAL_TC_EMIFS_CS2_CONFIG_PRELIM
        str r1, [r0]
        ldr r0, REG_TC_EMIFF_SDRAM_CONFIG
        ldr r1, VAL_TC_EMIFF_SDRAM_CONFIG
        str r1, [r0]
        ldr r0, REG_TC_EMIFF_MRS
        ldr r1, VAL_TC_EMIFF_MRS
        str r1, [r0]
        
        mov r0,#0x1800
again2:        
        subs r0,r0,#0x1
        bne again2
        FAKE_LED_MACRO(19)

 // Next, Enable the RS232 Line Drivers in the FPGA.
 // Also, power on the audio CODEC's amplifier here,
 // which will make a noise on the audio output.
 // This is done here instead of in the kernel so there
 // isn't a loud popping noise at the start of each
 // song.
 // Also, disable the CODEC's clocks.
 // omap1510-HelenP1 [specific]
        ldr r0, REG_FPGA_POWER
        mov r1, #0
        ldr r2, REG_FPGA_DIP_SWITCH
        ldrb r3, [r2]
        cmp r3, #0x8
        movne r1, #0x62     // Enable the RS232 Line Drivers in the EPLD
        strb r1, [r0]
        ldr r0, REG_FPGA_AUDIO
        mov r1, #0x0     // Disable sound driver (CODEC clocks)
        strb r1, [r0]
                 
        mov r0, #0x1800
again0:        
        subs r0, r0, #0x1
        bne again0
        FAKE_LED_MACRO(20)

// Init RHEA
// ----------        
        ldr r1, V_0x0000ff22
        mov r0, #0x0
        str r1, [r0]   // yep, that's really a write to address 0x00000000.

// *revisit-skranz* is needed?