var_io.h

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#ifndef CYGONCE_HAL_VAR_IO_H
#define CYGONCE_HAL_VAR_IO_H
//=============================================================================
//
//      var_io.h
//
//      Variant specific registers
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Nick Garnett <[e-mail]>
// Copyright (C) 2005, 2006 Andrew Lunn ([e-mail]>
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   jskov
// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, asl, John Eigelaar
// Date:        2001-07-12
// Purpose:     AT91 variant specific registers
// Description: 
// Usage:       #include <cyg/hal/var_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <cyg/hal/plf_io.h>

//=============================================================================
// USART

#ifndef AT91_USART0
#define AT91_USART0 0xFFFD0000
#endif

#ifndef AT91_USART1
#define AT91_USART1 0xFFFCC000
#endif

#define AT91_US_CR  0x00  // Control register
#define AT91_US_CR_RxRESET (1<<2)
#define AT91_US_CR_TxRESET (1<<3)
#define AT91_US_CR_RxENAB  (1<<4)
#define AT91_US_CR_RxDISAB (1<<5)
#define AT91_US_CR_TxENAB  (1<<6)
#define AT91_US_CR_TxDISAB (1<<7)
#define AT91_US_CR_RSTATUS (1<<8)
#define AT91_US_CR_STTTO   (1<<11)
#define AT91_US_MR  0x04  // Mode register
#define AT91_US_MR_CLOCK   4
#define AT91_US_MR_CLOCK_MCK  (0<<AT91_US_MR_CLOCK)
#define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
#define AT91_US_MR_CLOCK_SCK  (2<<AT91_US_MR_CLOCK)
#define AT91_US_MR_LENGTH  6
#define AT91_US_MR_LENGTH_5   (0<<AT91_US_MR_LENGTH)
#define AT91_US_MR_LENGTH_6   (1<<AT91_US_MR_LENGTH)
#define AT91_US_MR_LENGTH_7   (2<<AT91_US_MR_LENGTH)
#define AT91_US_MR_LENGTH_8   (3<<AT91_US_MR_LENGTH)
#define AT91_US_MR_SYNC    8
#define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)
#define AT91_US_MR_SYNC_SYNC  (1<<AT91_US_MR_SYNC)
#define AT91_US_MR_PARITY  9
#define AT91_US_MR_PARITY_EVEN  (0<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_ODD   (1<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_MARK  (3<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_NONE  (4<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)
#define AT91_US_MR_STOP   12
#define AT91_US_MR_STOP_1       (0<<AT91_US_MR_STOP)
#define AT91_US_MR_STOP_1_5     (1<<AT91_US_MR_STOP)
#define AT91_US_MR_STOP_2       (2<<AT91_US_MR_STOP)
#define AT91_US_MR_MODE   14
#define AT91_US_MR_MODE_NORMAL  (0<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE_ECHO    (1<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE_LOCAL   (2<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE_REMOTE  (3<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE9  17
#define AT91_US_MR_CLKO   18
#define AT91_US_IER 0x08  // Interrupt enable register
#define AT91_US_IER_RxRDY   (1<<0)  // Receive data ready
#define AT91_US_IER_TxRDY   (1<<1)  // Transmitter ready
#define AT91_US_IER_RxBRK   (1<<2)  // Break received
#define AT91_US_IER_ENDRX   (1<<3)  // Rx end
#define AT91_US_IER_ENDTX   (1<<4)  // Tx end
#define AT91_US_IER_OVRE    (1<<5)  // Rx overflow
#define AT91_US_IER_FRAME   (1<<6)  // Rx framing error
#define AT91_US_IER_PARITY  (1<<7)  // Rx parity
#define AT91_US_IER_TIMEOUT (1<<8)  // Rx timeout
#define AT91_US_IER_TxEMPTY (1<<9)  // Tx empty
#define AT91_US_IDR 0x0C  // Interrupt disable register
#define AT91_US_IMR 0x10  // Interrupt mask register
#define AT91_US_CSR 0x14  // Channel status register
#define AT91_US_CSR_RxRDY 0x01 // Receive data ready
#define AT91_US_CSR_TxRDY 0x02 // Transmit ready
#define AT91_US_CSR_RXBRK 0x04 // Transmit ready
#define AT91_US_CSR_ENDRX 0x08 // Transmit ready
#define AT91_US_CSR_ENDTX 0x10 // Transmit ready
#define AT91_US_CSR_OVRE  0x20 // Overrun error
#define AT91_US_CSR_FRAME 0x40 // Framing error
#define AT91_US_CSR_TIMEOUT 0x80 // Timeout
#define AT91_US_RHR 0x18  // Receive holding register
#define AT91_US_THR 0x1C  // Transmit holding register
#define AT91_US_BRG 0x20  // Baud rate generator
#define AT91_US_RTO 0x24  // Receive time out
#define AT91_US_TTG 0x28  // Transmit timer guard

// PDC US registers may have different addresses in at91 targets (i.e jtst)
#ifndef AT91_US_RPR
#define AT91_US_RPR 0x30  // Receive pointer register
#endif

#ifndef AT91_US_RCR
#define AT91_US_RCR 0x34  // Receive counter register
#endif

#ifndef AT91_US_TPR
#define AT91_US_TPR 0x38  // Transmit pointer register
#endif

#ifndef AT91_US_TCR
#define AT91_US_TCR 0x3c  // Transmit counter register
#endif

// PDC Control register bits
#define AT91_US_PTCR_RXTEN  (1 << 0)
#define AT91_US_PTCR_RXTDIS (1 << 1)
#define AT91_US_PTCR_TXTEN  (1 << 8)
#define AT91_US_PTCR_TXTDIS (1 << 9)

// macro could be different from target to target (i.e jtst)
#ifndef AT91_US_BAUD
#define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
#endif
//=============================================================================
// PIO

#ifndef AT91_PIO
#define AT91_PIO      0xFFFF0000
#endif

#define AT91_PIN(_ctrl_, _periph_, _pin_) \
  ((_ctrl_ << 16) | (_periph_ << 8) | (_pin_))

#define AT91_PIO_PER  0x00  // PIO enable
#define AT91_PIO_PDR  0x04  // PIO disable
#define AT91_PIO_PSR  0x08  // PIO status

// GPIO pins on PIO A.
#define AT91_GPIO_PA0       AT91_PIN(0,0, 0)
#define AT91_GPIO_PA1       AT91_PIN(0,0, 1)
#define AT91_GPIO_PA2       AT91_PIN(0,0, 2)
#define AT91_GPIO_PA3       AT91_PIN(0,0, 3)
#define AT91_GPIO_PA4       AT91_PIN(0,0, 4)
#define AT91_GPIO_PA5       AT91_PIN(0,0, 5)
#define AT91_GPIO_PA6       AT91_PIN(0,0, 6)
#define AT91_GPIO_PA7       AT91_PIN(0,0, 7)
#define AT91_GPIO_PA8       AT91_PIN(0,0, 8)
#define AT91_GPIO_PA9       AT91_PIN(0,0, 9)
#define AT91_GPIO_PA10      AT91_PIN(0,0,10)
#define AT91_GPIO_PA11      AT91_PIN(0,0,11)
#define AT91_GPIO_PA12      AT91_PIN(0,0,12)
#define AT91_GPIO_PA13      AT91_PIN(0,0,13)
#define AT91_GPIO_PA14      AT91_PIN(0,0,14)
#define AT91_GPIO_PA15      AT91_PIN(0,0,15)
#define AT91_GPIO_PA16      AT91_PIN(0,0,16)
#define AT91_GPIO_PA17      AT91_PIN(0,0,17)
#define AT91_GPIO_PA18      AT91_PIN(0,0,18)
#define AT91_GPIO_PA19      AT91_PIN(0,0,19)
#define AT91_GPIO_PA20      AT91_PIN(0,0,20)
#define AT91_GPIO_PA21      AT91_PIN(0,0,21)
#define AT91_GPIO_PA22      AT91_PIN(0,0,22)
#define AT91_GPIO_PA23      AT91_PIN(0,0,23)
#define AT91_GPIO_PA24      AT91_PIN(0,0,24)
#define AT91_GPIO_PA25      AT91_PIN(0,0,25)
#define AT91_GPIO_PA26      AT91_PIN(0,0,26)
#define AT91_GPIO_PA27      AT91_PIN(0,0,27)
#define AT91_GPIO_PA28      AT91_PIN(0,0,28)
#define AT91_GPIO_PA29      AT91_PIN(0,0,29)
#define AT91_GPIO_PA30      AT91_PIN(0,0,30)
#define AT91_GPIO_PA31      AT91_PIN(0,0,31)

#ifdef AT91_PIOB
// GPIO pins on PIOB.
#define AT91_GPIO_PB0       AT91_PIN(1,0, 0)
#define AT91_GPIO_PB1       AT91_PIN(1,0, 1)
#define AT91_GPIO_PB2       AT91_PIN(1,0, 2)
#define AT91_GPIO_PB3       AT91_PIN(1,0, 3)
#define AT91_GPIO_PB4       AT91_PIN(1,0, 4)
#define AT91_GPIO_PB5       AT91_PIN(1,0, 5)
#define AT91_GPIO_PB6       AT91_PIN(1,0, 6)
#define AT91_GPIO_PB7       AT91_PIN(1,0, 7)
#define AT91_GPIO_PB8       AT91_PIN(1,0, 8)
#define AT91_GPIO_PB9       AT91_PIN(1,0, 9)
#define AT91_GPIO_PB10      AT91_PIN(1,0,10)
#define AT91_GPIO_PB11      AT91_PIN(1,0,11)
#define AT91_GPIO_PB12      AT91_PIN(1,0,12)
#define AT91_GPIO_PB13      AT91_PIN(1,0,13)
#define AT91_GPIO_PB14      AT91_PIN(1,0,14)
#define AT91_GPIO_PB15      AT91_PIN(1,0,15)
#define AT91_GPIO_PB16      AT91_PIN(1,0,16)
#define AT91_GPIO_PB17      AT91_PIN(1,0,17)
#define AT91_GPIO_PB18      AT91_PIN(1,0,18)
#define AT91_GPIO_PB19      AT91_PIN(1,0,19)
#define AT91_GPIO_PB20      AT91_PIN(1,0,20)
#define AT91_GPIO_PB21      AT91_PIN(1,0,21)
#define AT91_GPIO_PB22      AT91_PIN(1,0,22)
#define AT91_GPIO_PB23      AT91_PIN(1,0,23)
#define AT91_GPIO_PB24      AT91_PIN(1,0,24)
#define AT91_GPIO_PB25      AT91_PIN(1,0,25)
#define AT91_GPIO_PB26      AT91_PIN(1,0,26)
#define AT91_GPIO_PB27      AT91_PIN(1,0,27)
#define AT91_GPIO_PB28      AT91_PIN(1,0,28)
#define AT91_GPIO_PB29      AT91_PIN(1,0,29)
#define AT91_GPIO_PB30      AT91_PIN(1,0,30)
#define AT91_GPIO_PB31      AT91_PIN(1,0,31)
#endif //AT91_PIOB

#if defined(CYGHWR_HAL_ARM_AT91_M55800A)

#define AT91_TC_TCLK3       AT91_PIN(0,0, 0) // Timer 3 Clock signal
#define AT91_TC_TIOA3       AT91_PIN(0,0, 1) // Timer 3 Signal A
#define AT91_TC_TIOB3       AT91_PIN(0,0, 2) // Timer 3 Signal B
#define AT91_TC_TCLK4       AT91_PIN(0,0, 3) // Timer 4 Clock signal
#define AT91_TC_TIOA4       AT91_PIN(0,0, 4) // Timer 4 Signal A
#define AT91_TC_TIOB4       AT91_PIN(0,0, 5) // Timer 4 Signal B
#define AT91_TC_TCLK5       AT91_PIN(0,0, 6) // Timer 5 Clock signal
#define AT91_TC_TIOA5       AT91_PIN(0,0, 7) // Timer 5 Signal A
#define AT91_TC_TIOB5       AT91_PIN(0,0, 8) // Timer 5 Signal B
#define AT91_INT_IRQ0       AT91_PIN(0,0, 9) // External Interrupt 0
#define AT91_INT_IRQ1       AT91_PIN(0,0,10) // External Interrupt 1
#define AT91_INT_IRQ2       AT91_PIN(0,0,11) // External Interrupt 2
#define AT91_INT_IRQ3       AT91_PIN(0,0,12) // External Interrupt 3
#define AT91_INT_FIQ        AT91_PIN(0,0,13) // Fast Interrupt
#define AT91_USART_SCK0     AT91_PIN(0,0,14) // USART 0 Clock signal
#define AT91_USART_TXD0     AT91_PIN(0,0,15) // USART 0 transmit data
#define AT91_USART_RXD0     AT91_PIN(0,0,16) // USART 0 receive data
#define AT91_USART_SCK1     AT91_PIN(0,0,17) // USART 1 Clock signal
#define AT91_USART_TXD1     AT91_PIN(0,0,18) // USART 1 transmit data
#define AT91_USART_RXD1     AT91_PIN(0,0,19) // USART 1 receive data
#define AT91_USART_SCK2     AT91_PIN(0,0,20) // USART 2 Clock signal