hal_sa11x0.h

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//==========================================================================
//
//      hal_sa11x0.h
//
//      HAL misc board support definitions for StrongARM SA11x0
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: gthomas, dmoseley
// Date:         2000-04-04
// Purpose:      Platform register definitions
// Description:  
//
//####DESCRIPTIONEND####
//
//========================================================================*/

#ifndef __HAL_SA11X0_H__
#define __HAL_SA11X0_H__ 1

#ifdef __ASSEMBLER__

#define REG8_VAL(a)  (a)
#define REG16_VAL(a) (a)
#define REG32_VAL(a) (a)

#define REG8_PTR(a)  (a)
#define REG16_PTR(a) (a)
#define REG32_PTR(a) (a)

#else /* __ASSEMBLER__ */

#define REG8_VAL(a)  ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#define REG32_VAL(a) ((unsigned int)(a))

#define REG8_PTR(a)  ((volatile unsigned char *)(a))
#define REG16_PTR(a) ((volatile unsigned long *)(a))
#define REG32_PTR(a) ((volatile unsigned long *)(a))

#endif /* __ASSEMBLER__ */

/*
 * SA11X0 Default Memory Layout Definitions
 */
// Typically ROM, FLASH
#define SA11X0_ROM_BANK0_BASE                    (0)
#define SA11X0_ROM_BANK1_BASE                    (SA11X0_ROM_BANK0_BASE + SZ_128M)
#define SA11X0_ROM_BANK2_BASE                    (SA11X0_ROM_BANK1_BASE + SZ_128M)
#define SA11X0_ROM_BANK3_BASE                    (SA11X0_ROM_BANK2_BASE + SZ_128M)

// May be ROM, FLASH, SRAM, etc
#define SA11X0_ROM_BANK4_BASE                    (0x40000000)
#define SA11X0_ROM_BANK5_BASE                    (SA11X0_ROM_BANK4_BASE + SZ_128M)

// Typically DRAM
#define SA11X0_RAM_BANK0_BASE                    (0xC0000000)
#define SA11X0_RAM_BANK1_BASE                    (SA11X0_RAM_BANK0_BASE + SZ_128M)
#define SA11X0_RAM_BANK2_BASE                    (SA11X0_RAM_BANK1_BASE + SZ_128M)
#define SA11X0_RAM_BANK3_BASE                    (SA11X0_RAM_BANK2_BASE + SZ_128M)

#define SA11X0_ZEROS_BANK_BASE                   (SA11X0_RAM_BANK3_BASE + SZ_128M)

/*
 * SA11X0 Register Definitions
 */
#define SA11X0_REGISTER_BASE                     0x80000000
#define SA11X0_REGISTER(x)                       REG32_PTR(SA11X0_REGISTER_BASE + (x))

/*
 * SA-1100 Cache and MMU Definitions
 */
#define SA11X0_ICACHE_SIZE                       0x4000  // 16K
#define SA11X0_DCACHE_SIZE                       0x2000  // 8K
#define SA11X0_ICACHE_LINESIZE_BYTES             32
#define SA11X0_DCACHE_LINESIZE_BYTES             32
#define SA11X0_ICACHE_LINESIZE_WORDS             8
#define SA11X0_DCACHE_LINESIZE_WORDS             8
#define SA11X0_ICACHE_WAYS                       32
#define SA11X0_DCACHE_WAYS                       32
#define SA11X0_ICACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
                                                           ~(SA11X0_ICACHE_LINESIZE_BYTES - 1))
#define SA11X0_DCACHE_LINE_BASE(p)               REG32_PTR((unsigned long)(p) & \
                                                           ~(SA11X0_DCACHE_LINESIZE_BYTES - 1))

/*
 * SA-1100 Coprocessor 15 Extensions Register Definitions
 */
#ifdef __ASSEMBLER__
#  define SA11X0_READ_PROCESS_ID_REGISTER        c13
#  define SA11X0_WRITE_PROCESS_ID_REGISTER       c13
#  define SA11X0_READ_BREAKPOINT_REGISTER        c14
#  define SA11X0_WRITE_BREAKPOINT_REGISTER       c14
#  define SA11X0_TEST_CLOCK_AND_IDLE_REGISTER    c15
#else /* __ASSEMBLER__ */
#  define SA11X0_READ_PROCESS_ID_REGISTER        "c13"
#  define SA11X0_WRITE_PROCESS_ID_REGISTER       "c13"
#  define SA11X0_READ_BREAKPOINT_REGISTER        "c14"
#  define SA11X0_WRITE_BREAKPOINT_REGISTER       "c14"
#  define SA11X0_TEST_CLOCK_AND_IDLE_REGISTER    "c15"
#endif /* __ASSEMBLER__ */

/*
 * SA-1100 Process ID Virtual Address Mapping Definitions
 */
#ifdef __ASSEMBLER__
#  define SA11X0_ACCESS_PROC_ID_REGISTER_OPCODE  0x0
#  define SA11X0_ACCESS_PROC_ID_REGISTER_RM      c0
#else /* __ASSEMBLER__ */
#  define SA11X0_ACCESS_PROC_ID_REGISTER_OPCODE  "0x0"
#  define SA11X0_ACCESS_PROC_ID_REGISTER_RM      "c0"
#endif /* __ASSEMBLER__ */

#define SA11X0_PROCESS_ID_PID_MASK               0x7E000000

/*
 * SA-1100 Debug Support Definitions
 */
#ifdef __ASSEMBLER__
#  define SA11X0_ACCESS_DBAR_OPCODE              0x0
#  define SA11X0_ACCESS_DBAR_RM                  c0
#  define SA11X0_ACCESS_DBVR_OPCODE              0x0
#  define SA11X0_ACCESS_DBVR_RM                  c1
#  define SA11X0_ACCESS_DBMR_OPCODE              0x0
#  define SA11X0_ACCESS_DBMR_RM                  c2
#  define SA11X0_LOAD_DBCR_OPCODE                0x0
#  define SA11X0_LOAD_DBCR_RM                    c3
#else /* __ASSEMBLER__ */
#  define SA11X0_ACCESS_DBAR_OPCODE              "0x0"
#  define SA11X0_ACCESS_DBAR_RM                  "c0"
#  define SA11X0_ACCESS_DBVR_OPCODE              "0x0"
#  define SA11X0_ACCESS_DBVR_RM                  "c1"
#  define SA11X0_ACCESS_DBMR_OPCODE              "0x0"
#  define SA11X0_ACCESS_DBMR_RM                  "c2"
#  define SA11X0_LOAD_DBCR_OPCODE                "0x0"
#  define SA11X0_LOAD_DBCR_RM                    "c3"
#endif /* __ASSEMBLER__ */

#define SA11X0_DBCR_LOAD_WATCH_DISABLED          0x00000000
#define SA11X0_DBCR_LOAD_WATCH_ENABLED           0x00000001
#define SA11X0_DBCR_LOAD_WATCH_MASK              0x00000001
#define SA11X0_DBCR_STORE_ADDRESS_WATCH_DISABLED 0x00000000
#define SA11X0_DBCR_STORE_ADDRESS_WATCH_ENABLED  0x00000002
#define SA11X0_DBCR_STORE_ADDRESS_WATCH_MASK     0x00000002
#define SA11X0_DBCR_STORE_DATA_WATCH_DISABLED    0x00000000
#define SA11X0_DBCR_STORE_DATA_WATCH_ENABLED     0x00000004
#define SA11X0_DBCR_STORE_DATA_WATCH_MASK        0x00000004

#define SA11X0_IBCR_INSTRUCTION_ADDRESS_MASK     0xFFFFFFFC
#define SA11X0_IBCR_BREAKPOINT_DISABLED          0x00000000
#define SA11X0_IBCR_BREAKPOINT_ENABLED           0x00000001
#define SA11X0_IBCR_BREAKPOINT_ENABLE_MASK       0x00000001

/*
 * SA-1100 Test, Clock and Idle Control Definition
 */
#ifdef __ASSEMBLER__
#  define SA11X0_ICACHE_ODD_WORD_LOADING_OPCODE  0x1
#  define SA11X0_ICACHE_ODD_WORD_LOADING_RM      c1
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_OPCODE 0x1
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_RM     c2
#  define SA11X0_ICACHE_CLEAR_LFSR_OPCODE        0x1
#  define SA11X0_ICACHE_CLEAR_LFSR_RM            c4
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_OPCODE   0x1
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_RM       c8
#  define SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE   0x2
#  define SA11X0_ENABLE_CLOCK_SWITCHING_RM       c1
#  define SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE  0x2
#  define SA11X0_DISABLE_CLOCK_SWITCHING_RM      c2
#  define SA11X0_WAIT_FOR_INTERRUPT_OPCODE       0x2
#  define SA11X0_WAIT_FOR_INTERRUPT_RM           c8
#else /* __ASSEMBLER__ */
#  define SA11X0_ICACHE_ODD_WORD_LOADING_OPCODE  "0x1"
#  define SA11X0_ICACHE_ODD_WORD_LOADING_RM      "c1"
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_OPCODE "0x1"
#  define SA11X0_ICACHE_EVEN_WORD_LOADING_RM     "c2"
#  define SA11X0_ICACHE_CLEAR_LFSR_OPCODE        "0x1"
#  define SA11X0_ICACHE_CLEAR_LFSR_RM            "c4"
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_OPCODE   "0x1"
#  define SA11X0_MOVE_LFSR_TO_R14_ABORT_RM       "c8"
#  define SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE   "0x2"
#  define SA11X0_ENABLE_CLOCK_SWITCHING_RM       "c1"
#  define SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE  "0x2"
#  define SA11X0_DISABLE_CLOCK_SWITCHING_RM      "c2"
#  define SA11X0_WAIT_FOR_INTERRUPT_OPCODE       "0x2"
#  define SA11X0_WAIT_FOR_INTERRUPT_RM           "c8"
#endif /* __ASSEMBLER__ */


/*
 * SA11X0 IRQ Controller IRQ Numbers
 */
#define SA11X0_IRQ_MIN                           0
                                                 
#define SA11X0_IRQ_GPIO_0_EDGE_DETECT            0
#define SA11X0_IRQ_GPIO_1_EDGE_DETECT            1
#define SA11X0_IRQ_GPIO_2_EDGE_DETECT            2
#define SA11X0_IRQ_GPIO_3_EDGE_DETECT            3
#define SA11X0_IRQ_GPIO_4_EDGE_DETECT            4
#define SA11X0_IRQ_GPIO_5_EDGE_DETECT            5
#define SA11X0_IRQ_GPIO_6_EDGE_DETECT            6
#define SA11X0_IRQ_GPIO_7_EDGE_DETECT            7
#define SA11X0_IRQ_GPIO_8_EDGE_DETECT            8
#define SA11X0_IRQ_GPIO_9_EDGE_DETECT            9
#define SA11X0_IRQ_GPIO_10_EDGE_DETECT           10
#define SA11X0_IRQ_GPIO_ANY_EDGE_DETECT          11
#define SA11X0_IRQ_LCD_CONT_SERVICE_REQUEST      12