nano_misc.c

开放源码实时操作系统源码.

//==========================================================================
//
//      nano_misc.c
//
//      HAL misc board support code for StrongARM SA1110/nanoEngine
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: hmt
//               Travis C. Furrer <[e-mail]>
// Date:         2001-02-12
// Purpose:      HAL board support
// Description:  Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/

#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H

#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_arch.h>           // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h>           // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_sa11x0.h>         // Hardware definitions
#include <cyg/hal/nano.h>               // Platform specifics

#include <cyg/infra/diag.h>             // diag_printf

// All the MM table layout is here:
#include <cyg/hal/hal_mm.h>

#ifdef CYGPKG_IO_PCI
cyg_uint32 cyg_pci_window_real_base = 0;
#endif

#include <string.h> // memset

void
hal_mmu_init(void)
{
    unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
    unsigned long i;

#ifdef CYG_HAL_STARTUP_ROM
    // SDRAM Memory Sizing:
    //
    // The board can have 4 memory configurations:
    //
    //  * One 8Mb device on SDCS0 (with gaps <= A11 N/C in 8Mb devices)
    //  * Two 8Mb devices, SDCS0,SDCS1 (with gaps) making 16Mb
    //  * One 16Mb device on SDCS0
    //  * Two 16Mb devices on SDCS0,SDCS1 making 32Mb
    //
    // Gaps: the SDRAM setup and wiring are the same for both 8Mb and 16Mb
    // devices.  A11 of the SDRAM's addressing is not connected when 8Mb
    // devices are installed; the 8Mb device occupies 16Mb of space.  A11
    // on the SDRAM is the most significant bit below the two bank-select
    // bits, there are 4 banks each occupying 4Mb, so therefore in "real
    // money" it has the value 2Mb.
    //
    // SDCS0 maps to the 128Mb area 0xC00 Mb (0xC00000000)
    // SDCS1 maps to the 128Mb area 0xC80 Mb (0xC80000000)
    //
    // So therefore, if there are two 8Mb devices installed, we have memory
    // in these ranges:
    //
    //    0xC0000000...0xC01FFFFF
    //    0xC0400000...0xC05FFFFF
    //    0xC0800000...0xC09FFFFF
    //    0xC0C00000...0xC0DFFFFF
    //
    //    0xC8000000...0xC81FFFFF
    //    0xC8400000...0xC85FFFFF
    //    0xC8800000...0xC89FFFFF
    //    0xC8C00000...0xC8DFFFFF
    //
    // This function is currently executing on a stack in real memory
    // addresses, somewhere in that initial range 0xC0000000...0xC01FFFFF,
    // so we can probe other related addresses to discover how much memory
    // we really have, and then set up the Memory Map accordingly.

    typedef volatile cyg_uint32 *mptr; // for memory access
    typedef cyg_uint32 aptr;        // for arithmetic
    volatile int testmem[4] = {0};  // on my stack, ergo in base memory

    // Pointers to test memory, and into the possible gap:
    mptr basep =  &testmem[0];
    mptr basep2 = &testmem[1];
    mptr gapp =  (mptr)((2 * SZ_1M) | (aptr)basep);
        
    // And just look at any pair of words to discover whether there is
    // a 2nd device there.
    mptr dev2p = (mptr)((0xC80u * SZ_1M) | (aptr)basep);
    mptr dev2p2 = (mptr)(4 + (aptr)dev2p);

    // This is a pointer to where hal_dram_size is in physical memory,
    // since memory mapping is not yet set up:
    int *p_hdsize = (int *)((aptr)(&hal_dram_size) | (0xC00u *SZ_1M));
    int *p_hdtype = (int *)((aptr)(&hal_dram_type) | (0xC00u *SZ_1M));

    *p_hdsize = 0; // Initialize it to a bogus value here.
    *p_hdtype = 0x0108; // Initialize it to a bogus value here.
    
    // Equivalent of asserts for our assumptions, but too early to use
    // CYG_ASSERT( ..., "basep not in bank0 of device 0, lower half" );
    if ( 0xC0000000u >= (aptr)basep ) {
        *p_hdtype |= 1 << 16; // flag an error code
        goto breakout;
    }
    if ( 0xC0200000u < (aptr)basep ) {
        *p_hdtype |= 2 << 16;
        goto breakout;
    }
    
    // First confirm that the technique works for memory that's
    // definitely there!
    *basep  = 0x55667711;
    *basep2 = 0xCC33AA44;
    if ( 0x55667711 != *basep ||
         0xCC33AA44 != *basep2 ) {
        *p_hdtype |= 10 << 16;
        goto breakout;
    }
    // Now test writing to the gap...
    *gapp = 0xDD2288BB;
    if ( 0xCC33AA44 != *basep2 ) { // Should not be corrupted whatever
        *p_hdtype |= 20 << 16;
        goto breakout;
    }
    if ( 0xDD2288BB != *basep &&
         0x55667711 != *basep ) { // Should be one of those
        *p_hdtype |= 30 << 16;
        goto breakout;
    }

    if (0xDD2288BB == *basep)
        *p_hdtype = 8; // Lower byte is SDRAM size in Mb.
    else {
        // it could be 16Mb or 32Mb:
        basep2 = (mptr)((16 * SZ_1M) | (aptr)basep);
        *basep = 0xFF11AA00;
        *basep2 = 0x33557799;
        // (intersperse some other activity)
        testmem[2] += testmem[3];
        if ( 0xFF11AA00 != *basep &&
             0x33557799 != *basep ) { // Should be one of those
            *p_hdtype |= 40 << 16;
            goto breakout;
        }
        *p_hdtype = (0xFF11AA00 == *basep) ? 32 : 16;
    }

    // Now test whether dev2p stores data:
    *dev2p  = 0x11224488;
    *dev2p2 = 0x77BBDDEE;