📄 sa1100mm_misc.c
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//==========================================================================
//
// sa1100mm_misc.c
//
// HAL misc board support code for StrongARM SA1110/Multimedia
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: hmt, dmoseley
// Travis C. Furrer <furrer@mit.edu>
// Date: 2000-05-21
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_sa11x0.h> // Hardware definitions
#include <cyg/hal/sa1100mm.h> // Platform specifics
#include <cyg/infra/diag.h> // diag_printf
// All the MM table layout is here:
#include <cyg/hal/hal_mm.h>
#include <string.h> // memset
void
hal_mmu_init(void)
{
unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
unsigned long i;
/*
* Set the TTB register
*/
asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
/*
* Set the Domain Access Control Register
*/
i = ARM_ACCESS_DACR_DEFAULT;
asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
/*
* First clear all TT entries - ie Set them to Faulting
*/
memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
/* Actual Virtual Size Attributes Function */
/* Base Base MB cached? buffered? access permissions */
/* xxx00000 xxx00000 */
X_ARM_MMU_SECTION(0x000, 0x500, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
X_ARM_MMU_SECTION(0x080, 0x080, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
X_ARM_MMU_SECTION(0x100, 0x100, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA-1101 Development Board Registers */
X_ARM_MMU_SECTION(0x180, 0x180, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Ct8020 DSP */
X_ARM_MMU_SECTION(0x184, 0x184, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* XBusReg */
X_ARM_MMU_SECTION(0x188, 0x188, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegA */
X_ARM_MMU_SECTION(0x18C, 0x18C, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegB */
X_ARM_MMU_SECTION(0x190, 0x190, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD A */
X_ARM_MMU_SECTION(0x194, 0x194, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD B */
X_ARM_MMU_SECTION(0x200, 0x200, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets */
X_ARM_MMU_SECTION(0x800, 0x800, 1024, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
X_ARM_MMU_SECTION(0xC00, 0, 8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
X_ARM_MMU_SECTION(0xC00, 0xC00, 8, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
}
//
// Platform specific initialization
//
void
plf_hardware_init(void)
{
}
#include CYGHWR_MEMORY_LAYOUT_H
typedef void code_fun(void);
void sa1100mm_program_new_stack(void *func)
{
register CYG_ADDRESS stack_ptr asm("sp");
register CYG_ADDRESS old_stack asm("r4");
register code_fun *new_func asm("r0");
old_stack = stack_ptr;
stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
new_func = (code_fun*)func;
new_func();
stack_ptr = old_stack;
return;
}
// ------------------------------------------------------------------------
// EOF sa1100mm_misc.c
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