hal_platform_setup.h

开放源码实时操作系统源码.

// Initialize memory interfaces. (ROM, SRAM, Flash, DRAM, etc)
//
// SA1100 Multimedia memory is as follows:
//   ROM     128K (assuming 32 bit accesses)
//   Flash   4M (assuming 32 bit accesses)
//   RAM     8M
//
// From SA11X0 Manual, Section 10.7.1:
//
//  The following flow should be followed when coming out of
//  reset, whether for sleep or power-up:
//
//    - Read boot ROM and write to memory configuration
//      registers, but do not enable DRAM banks.
//
//    - If necessary, finish any DRAM power-up wait period
//      (usually about 100us).
//
//    - If coming out of sleep, see Section 9.5, Power
//      Manager on page 9-26 on how to release the nCAS and
//      nRAS pins from their self-refresh state.
//
//    - If coming out of sleep, wait the DRAM-specific
//      post-self-refresh precharge period before issuing
//      a new DRAM transaction.
//
//    - If power-on reset, perform the number of
//      initialization refreshes required by the specific
//      DRAM part by reading disabled banks. A read from
//      any disabled bank will refresh all four banks.
//
//    - Enable DRAM banks by setting MDCNFG:DE3:0.
//
#define DRAM_CONFIG_VALUE      (SA11X0_DRAM_REFRESH_INTERVAL(312)              | \
                                SA11X0_DATA_INPUT_LATCH_CAS_PLUS_THREE         | \
                                SA11X0_DRAM_CAS_BEFORE_RAS(5)                  | \
                                SA11X0_DRAM_RAS_PRECHARGE(4)                   | \
                                SA11X0_DRAM_CLOCK_CPU_CLOCK                    | \
                                SA11X0_DRAM_ROW_ADDRESS_BITS_11                | \
                                SA11X0_DRAM_BANK_0_ENABLED                     | \
                                SA11X0_DRAM_BANK_1_DISABLED                    | \
                                SA11X0_DRAM_BANK_2_DISABLED                    | \
                                SA11X0_DRAM_BANK_3_DISABLED)

#define DRAM_CAS0_WAVEFORM     0xF0F0F00F
#define DRAM_CAS1_WAVEFORM     0XF0F0F0F0
#define DRAM_CAS2_WAVEFORM     0xFFFFFFF0

#define BANK_0_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
                               SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS             | \
                               SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
                               SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
                               SA11X0_STATIC_ROM_RECOVERY(0x7)
#define BANK_1_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
                               SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS             | \
                               SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
                               SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
                               SA11X0_STATIC_ROM_RECOVERY(0x7)
#define STATIC_CONTROL_0_VALUE (SA11X0_STATIC_ROM_BANK_0(BANK_0_CONTROL_VALUE) | \
                                SA11X0_STATIC_ROM_BANK_1(BANK_1_CONTROL_VALUE))

#define BANK_2_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
                               SA11X0_STATIC_ROM_BUS_WIDTH_16_BITS             | \
                               SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
                               SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
                               SA11X0_STATIC_ROM_RECOVERY(0x7)
#define BANK_3_CONTROL_VALUE   SA11X0_STATIC_ROM_TYPE_FLASH                    | \
                               SA11X0_STATIC_ROM_BUS_WIDTH_32_BITS             | \
                               SA11X0_STATIC_ROM_DELAY_FIRST_ACCESS(0x1F)      | \
                               SA11X0_STATIC_ROM_DELAY_NEXT_ACCESS(0x1F)       | \
                               SA11X0_STATIC_ROM_RECOVERY(0x7)
#define STATIC_CONTROL_1_VALUE (SA11X0_STATIC_ROM_BANK_2(BANK_2_CONTROL_VALUE) | \
                                SA11X0_STATIC_ROM_BANK_3(BANK_3_CONTROL_VALUE))

        .macro  _init_MEM_INTERFACES
        /*
         * Initialize the DRAM Controller
         */
        ldr     r0, =SA11X0_DRAM_CONFIGURATION
        ldr     r1, =DRAM_CONFIG_VALUE
        str     r1, [r0]
                
        ldr     r0, =SA11X0_DRAM0_CAS_0
        ldr     r1, =DRAM_CAS0_WAVEFORM
        str     r1, [r0]
                
        ldr     r0, =SA11X0_DRAM0_CAS_1
        ldr     r1, =DRAM_CAS1_WAVEFORM
        str     r1, [r0]
                
        ldr     r0, =SA11X0_DRAM0_CAS_2
        ldr     r1, =DRAM_CAS2_WAVEFORM
        str     r1, [r0]
                
        ldr     r0, =SA11X0_STATIC_CONTROL_0

        /*
         * Get the reset ROM setup
         */
        ldr     r1, [r0]

        /*
         * Get the 16/32 bit setting to merge into the appropriate
         * register values later on.
         */
        and     r1, r1, #SA11X0_STATIC_ROM_BUS_WIDTH_MASK

        /*
         * MSC0 - bank 0 ROM, bank 1 FLASH
         */
        ldr     r2, =STATIC_CONTROL_0_VALUE
        orr     r1, r1, r2

        str     r1, [r0]

        /*
         * MSC1 - bank 2 SRAM, bank 3 REG
         */
        ldr     r0, =SA11X0_STATIC_CONTROL_1
        ldr     r1, =STATIC_CONTROL_1_VALUE
        str     r1, [r0]

        /*
         * Delay to let the DRAM warm up
         */
        ldr     r0, =0x200
0:      subs    r0, r0, #1
        bne     0b

        .endm

        
        .macro  _platform_setup1
        nop                                                               
        nop                                                               
        nop                                                               
        nop                                                               
        nop                                                               
        nop                                                               
        nop                                                               
        nop                                                               
        nop                                                               

        _init_GPIO
        _init_HEX_DISPLAY               /* this is flaky sometimes */       
        _init_HEX_DISPLAY               /* so do it twice just in case */   

        _set_LEDS 0x15

        _init_PERIPHERAL_PINS                                               
        _set_LEDS 0x13
                                                                           
        _set_CLOCK_FREQUENCY                                                
        _enable_CLOCK_SWITCHING                                             
        _set_LEDS 0x12
                                                                           
        _init_MEM_INTERFACES                                                
        _set_LEDS 0x11
                                                                           
        // Set up a stack [for calling C code]
        ldr     r1,=__startup_stack
        ldr     r2,=SA11X0_RAM_BANK0_BASE
        orr     sp,r1,r2

        // Create MMU tables
        bl      hal_mmu_init

        _set_LEDS 0x09
        // Enable MMU
        ldr     r2,=10f
        ldr     r1,=MMU_Control_Init|MMU_Control_M
        mcr     MMU_CP,0,r1,MMU_Control,c0
        mov     pc,r2    /* Change address spaces */

        nop
        nop
        nop
10:
        _set_LEDS 0x08

        .endm
                        
#else // STARTUP_ROM        
#define PLATFORM_SETUP1
#endif

/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */