var_io.h

开放源码实时操作系统源码.

//
// *********************************************************************/

#define MAC7100_PIM_BASE  (0xFC0E8000)

#define MAC7100_PORT_A_OFFSET (0x000)
#define MAC7100_PORT_B_OFFSET (0x040)
#define MAC7100_PORT_C_OFFSET (0x080)
#define MAC7100_PORT_D_OFFSET (0x0C0)
#define MAC7100_PORT_E_OFFSET (0x100)
#define MAC7100_PORT_F_OFFSET (0x140)
#define MAC7100_PORT_G_OFFSET (0x180)
#define MAC7100_PORT_H_OFFSET (0x1C0)
#define MAC7100_PORT_I_OFFSET (0x200)

// PORT Pin Configuration Registers 
#define MAC7100_PIM_CONFIG(port,pin)  (MAC7100_PIM_BASE+port+((pin)*2)) 
// Port Wide Interrupt Flag Register 
#define MAC7100_PIM_PORTIFR(port)     (MAC7100_PIM_BASE+port+0x20) 
// Port Wide Data Read/Write Register 
#define MAC7100_PIM_PORTDATA(port)    (MAC7100_PIM_BASE+port+0x24) 
// Port Wide Input Register 
#define MAC7100_PIM_PORTIR(port)      (MAC7100_PIM_BASE+port+0x26) 
// Port Pin Data Registers 
#define MAC7100_PIM_DATA(port,pin)    (MAC7100_PIM_BASE+port+0x28+pin) 

// Global Interrupt Status Register 
#define MAC7100_PIM_GLBLINT    (MAC7100_PIM_BASE+0x03C0) 
// PIM Configuration Register 
#define MAC7100_PIM_PIMCONFIG  (MAC7100_PIM_BASE+0x03C2) 
// TDI Pin Configuration Register 
#define MAC7100_PIM_CONFIG_TDI (MAC7100_PIM_BASE+0x03C4) 
// TDO Pin Configuration Register 
#define MAC7100_PIM_CONFIG_TDO (MAC7100_PIM_BASE+0x03C6) 
// TMS Pin Configuration Register 
#define MAC7100_PIM_CONFIG_TMS (MAC7100_PIM_BASE+0x03C8) 
// TCK Pin Configuration Register 
#define MAC7100_PIM_CONFIG_TCK (MAC7100_PIM_BASE+0x03CA) 
// TA Pin Configuration Register 
#define MAC7100_PIM_CONFIG_TA  (MAC7100_PIM_BASE+0x03CC) 

// Bit definitions and macros for PIM_PA_CONFIGn 
//  Pin Interrupt Flag Register 
#define MAC7100_PIM_PIFR            (0x0001)       
//  Pin Interrupt Enable Register 
#define MAC7100_PIM_PIER            (0x0002)       
//  Pull-up/down Enable Register 
#define MAC7100_PIM_PULL(x)         (((x)&0x0003)<<2)    
//  Reduced Drive Strength Register 
#define MAC7100_PIM_RDR             (0x0010)       
//  Open Drain Enable Register 
#define MAC7100_PIM_ODER            (0x0020)       
//  Data Direction Register 
#define MAC7100_PIM_DDR             (0x0040)       
#define MAC7100_PIM_MODE            (0x0080)       
#define MAC7100_PIM_MODE_PERIPHERAL MAC7100_PIM_MODE

// Bit definitions and macros for PIM_GLBLINT 
//  Interrupt Pending 
#define MAC7100_PIM_INT_PENDING(x)  (((x)&0x01FF)<<0)    

// Bit definitions and macros for PIM_PIMCONFIG 
//  Clock Enable for the EIM module 
#define MAC7100_PIM_PORTHSEL        (0x0001)       
//  Port H Select 
#define MAC7100_PIM_EIMCLKEN        (0x0002)       

#define MAC7100_PIM_PORT32IR(port32ir)  (MAC7100_PIM_BASE+0x03E0+port32ir)

#define MAC7100_PIM_PORT32IR_AB (0x00)
#define MAC7100_PIM_PORT32IR_CD (0x04)
#define MAC7100_PIM_PORT32IR_EF (0x08)
#define MAC7100_PIM_PORT32IR_GH (0x0C)
#define MAC7100_PIM_PORT32IR_BC (0x10)
#define MAC7100_PIM_PORT32IR_DE (0x14)
#define MAC7100_PIM_PORT32IR_FG (0x18)
#define MAC7100_PIM_PORT32IR_HI (0x1C)


// ********************************************************************
//
// CRG Module
//
// ********************************************************************

// Register read/write macros 
#define MAC7100_CRG_BASE   0xFC088000 // SYNR - Synthesizer Register 
#define MAC7100_CRG_SYNR   0xFC088000 // SYNR - Synthesizer Register 
#define MAC7100_CRG_REFDV  0xFC088001 // REFDV - Reference Divider Register 
#define MAC7100_CRG_CTFLG  0xFC088002 // CTFLG - Test Flags Register (reserved)
#define MAC7100_CRG_CRGFLG 0xFC088003 // CRGFLG - Flags Register 
#define MAC7100_CRG_CRGINT 0xFC088004 // CRGINT - Interrupt Enable Register 
#define MAC7100_CRG_CLKSEL 0xFC088005 // CLKSEL - Clock Select Register 
#define MAC7100_CRG_PLLCTL 0xFC088006 // PLLCTL - PLL Control Register 
#define MAC7100_CRG_SDMCTL 0xFC088007 // SDMCTL - STOP/DOZE Control Register 
#define MAC7100_CRG_BDMCTL 0xFC088008 // BDMCTL - BDM Control Register 
#define MAC7100_CRG_FORBYP 0xFC088009 // FORBYP - Force and Bypass Test 
#define MAC7100_CRG_CTCTL  0xFC08800A // CTCTL - Test Control Register (resvd) 

// Bit definitions and macros for CRG_SYNR 
#define MAC7100_CRG_SYN(x) (((x)&0x3F)<<0)  //  Synthesizer Count value 

// Bit definitions and macros for CRG_REFDV 
#define MAC7100_CRG_REFD(x) (((x)&0x0F)<<0)  //Reference divider 

// Bit definitions and macros for CRG_CRGFLG 
#define MAC7100_CRG_SCM     (0x01)         //Self Clock Mode Status 
#define MAC7100_CRG_SCMIF   (0x02)         //Self Clock Mode Interrupt Flag 
#define MAC7100_CRG_TRACK   (0x04)         //Track Status 
#define MAC7100_CRG_LOCK    (0x08)         //Lock Status 
#define MAC7100_CRG_LOCKIF  (0x10)         //PLL Lock Interrupt Flag 
#define MAC7100_CRG_LVRF    (0x20)         //Low Voltage Reset Flag 
#define MAC7100_CRG_PORF    (0x40)         //Power on Reset Flag 
#define MAC7100_CRG_STPEF   (0x80)         //Stop Entry Flag 

// Bit definitions and macros for CRG_CRGINT 
#define MAC7100_CRG_SCMIE   (0x02)         //Self Clock Mode Interrupt Enable 
#define MAC7100_CRG_LOCKIE  (0x10)         //Lock Interrupt Enable 

// Bit definitions and macros for CRG_CLKSEL 
#define MAC7100_CRG_SWTDOZE  (0x01)         //SWT stops in Doze Mode 
#define MAC7100_CRG_RTIDOZE  (0x02)         /*  RTI stops in Doze Mode */
#define MAC7100_CRG_PLLDOZE  (0x08)         /*  PLL stops in Doze Mode */
#define MAC7100_CRG_DOZE_ROA (0x10)         /*  Reduced Osc Amp in Doze Mode */
#define MAC7100_CRG_PSTP     (0x40)         /*  Pseudo Stop */
#define MAC7100_CRG_PLLSEL   (0x80)         /*  PLL Select */

// Bit definitions and macros for CRG_PLLCTL 
#define MAC7100_CRG_SCME     (0x01)         //Self Clock Mode Enable 
#define MAC7100_CRG_PWE      (0x02)         //SWT Enable during Pseudo Stop 
#define MAC7100_CRG_PRE      (0x04)         //RTI Enable during Pseudo Stop 
#define MAC7100_CRG_FSTWKP   (0x08)         //Fast Wake-up from Full Stop Bit 
#define MAC7100_CRG_ACQ      (0x10)         //Acquisition 
#define MAC7100_CRG_AUTO     (0x20)         //Automatic Bandwidth Control 
#define MAC7100_CRG_PLLON    (0x40)         //Phase Lock Loop On 
#define MAC7100_CRG_CME      (0x80)         //Clock Monitor Enable 

// Bit definitions and macros for CRG_SDMCTL 
#define MAC7100_CRG_STOP     (0x01)         //STOP mode 
#define MAC7100_CRG_DOZE     (0x02)         //DOZE mode 

// Bit definitions and macros for CRG_BDMCTL 
#define MAC7100_CRG_RSBCK    (0x40)         //SWT & RTI stop in Active BDM mode


// *********************************************************************
//
// MCM Module
//
// *********************************************************************

// Register read/write macros
#define MAC7100_MCM_PCT    0xFC040000 // 
#define MAC7100_MCM_REV    0xFC040002 // 
#define MAC7100_MCM_AMC    0xFC040004 // 
#define MAC7100_MCM_ASC    0xFC040006 // 
#define MAC7100_MCM_IMC    0xFC040008 // 
// MRSR - Miscellaneous Reset Status Register 
#define MAC7100_MCM_MRSR   0xFC04000F 
// MWCR - Miscellaneous Wakeup Control Register 
#define MAC7100_MCM_MWCR   0xFC040013 
// MSWTCR - Miscellaneous Software Watchdog Timer Control Register 
#define MAC7100_MCM_MSWTCR 0xFC040016 
// MSWTSR - Miscellaneous Software Watchdog Timer Service Register 
#define MAC7100_MCM_MSWTSR 0xFC04001B 
// MSWTIR - Miscellaneous Software Watchdog Timer Interrupt Register 
#define MAC7100_MCM_MSWTIR 0xFC04001F 
// AAMR - AXBS Address Map Register 
#define MAC7100_MCM_AAMR   0xFC040020 
// CFADR - Core Fault Address Register 
#define MAC7100_MCM_CFADR  0xFC040070 
// CFLOC - Core Fault Location Register 
#define MAC7100_MCM_CFLOC  0xFC040076 
// CFATR - Core Fault Attributes Register 
#define MAC7100_MCM_CFATR  0xFC040077 
// CFDTR - Core Fault Data Register 
#define MAC7100_MCM_CFDTR  0xFC04007C 

// Bit definitions and macros for MCM_AMC 

//  AXBS Master Configuration 
#define MAC7100_MCM_AXMC(x)    (((x)&0x00FF)<<0)    

// Bit definitions and macros for MCM_ASC 
//  AXBS Slave Configuration 
#define MAC7100_MCM_AXSC(x)    (((x)&0x00FF)<<0)    
#define MAC7100_MCM_DP64       (0x8000)             //  64-bit Datapath 

// Bit definitions and macros for MCM_MRSR 
#define MAC7100_MCM_SWTR       (0x20)         //  Watchdog Timer Reset 
#define MAC7100_MCM_DIR        (0x40)         //  Device Input Reset 
#define MAC7100_MCM_POR        (0x80)         //  Power-On Reset 

// Bit definitions and macros for MCM_MWCR 
#define MAC7100_MCM_PRILVL(x)  (((x)&0x0F)<<0)  //  Interrupt Priority Level 
#define MAC7100_MCM_ENBWCR     (0x80)           //  Enable WCR

// Bit definitions and macros for MCM_MSWTCR 
#define MAC7100_MCM_SWT(x)     (((x)&0x001F)<<0)  //  Watchdog Time-Out Period 
#define MAC7100_MCM_SWRI(x)    (((x)&0x0003)<<5)  //  Watchdog Reset/Interrupt 
#define MAC7100_MCM_SWE        (0x0080)       //  Watchdog Enable 
#define MAC7100_MCM_SWRWH      (0x0100)       //  Watchdog Run While Halted 
#define MAC7100_MCM_SWCIN16    (0x0200)       //  Force SWT CarryIn16 
#define MAC7100_MCM_RO         (0x8000)       //  Read-Only 

// Bit definitions and macros for MCM_MSWTIR 
#define MAC7100_MCM_SWTIC      (0x01)         //  Watchdog Interrupt Flag 

// Bit definitions and macros for MCM_AAMR


//  Address 0 Slave Number 
#define MAC7100_MCM_ASLAVE(adr_reg,sl_n) (((sl_n)&0x00000007)<<(adr_reg*4) 
//  Enable Address Region 0 
#define MAC7100_MCM_EA(adr_reg)        (0x00000008<<(adr_reg*4))  

// Bit definitions and macros for MCM_CFLOC 
#define MAC7100_MCM_LOCALERR               (0x80)  //  Bus Error Indicator 

// Bit definitions and macros for MCM_CFATR 
//  Protection fault type 
#define MAC7100_MCM_PROTECTION(x)          (((x)&0x0F)<<0)  
//  8-16-32-64-bit core access 
#define MAC7100_MCM_SIZE(x)                (((x)&0x07)<<4)  
//  Core read/write access 
#define MAC7100_MCM_WRITE                  (0x80)         

//=============================================================================
// FIQ interrupt vector which is shared by all HAL variants.

#define CYGNUM_HAL_INTERRUPT_FIQ 0
#endif // CYGONCE_HAL_VAR_IO_H
//-----------------------------------------------------------------------------
// end of var_io.h