📄 hal_platform_setup.h

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	str	r2,[r1]				
	ldr	r1,=MEMCFG2			
	ldr	r2,=0x00001F13			
	str	r2,[r1]
        .endm
#else
#ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_EP7209
// No DRAM controller
        .macro  INIT_MEMORY_CONFIG
/* Initialize memory configuration */
	ldr	r1,=MEMCFG1
	ldr	r2,=0x8200A080
	str	r2,[r1]
	ldr	r1,=MEMCFG2
	ldr	r2,=0xFEFC0000
	str	r2,[r1]
        .endm
#else // CYGHWR_HAL_ARM_EDB7XXX_VARIANT = EP7211, EP7212
        .macro  INIT_MEMORY_CONFIG
/* Initialize memory configuration */
	ldr	r1,=MEMCFG1
	ldr	r2,=0x8200A080
	str	r2,[r1]
	ldr	r1,=MEMCFG2
	ldr	r2,=0xFEFC0000
	str	r2,[r1]
	ldr	r1,=DRFPR
	ldr	r2,=0x81	/* DRAM refresh = 64KHz */
	strb	r2,[r1]
        .endm
#endif
#endif

#if defined(CYGSEM_HAL_STATIC_MMU_TABLES)
#define PLATFORM_SETUP1                          \
        INIT_MEMORY_CONFIG                      ;\
        ldr     r1,=_MMU_table-0xE0000000       ;\
        MMU_INITIALIZE                          ;\
        RELOCATE_TEXT_SEGMENT

#define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h>

#else
// MMU tables placed in DRAM

#if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
// Note: The DRAM on this board is very irregular in that every
// other 256K piece is missing.  E.g. only these [physical]
// addresses are valid:
//   0xC0000000..0xC003FFFF
//   0xC0080000..0xC00BFFFF
//   0xC0200000..0xC023FFFF    Note the additional GAP!
//      etc.
//   0xC0800000..0xC083FFFF    Note the additional GAP!
//   0xC0880000..0xC08CFFFF
//   0xC0A00000..0xC0A3FFFF
//      etc.
// The MMU mapping code takes this into consideration and creates
// a continuous logical map for the DRAM.
        .macro  MAP_DRAM
/* Map DRAM */
	ldr	r3,=DRAM_LA_START
	ldr	r4,=DRAM_LA_END
	ldr	r5,=DRAM_PA
/* 0x00000000..0x000FFFFF */
	mov	r6,r2		/* Set up page table descriptor */
	ldr	r7,=MMU_L1_TYPE_Page
	orr	r6,r6,r7
	str	r6,[r1],#4	/* Store PTE, update pointer */
10:	mov	r6,r5		/* Build page table entry */
	ldr	r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
	orr	r6,r6,r7
	ldr	r7,=MMU_PAGE_SIZE
	str	r6,[r2],#4	/* Next page */
	add	r3,r3,r7
	add	r5,r5,r7
	ldr	r8,=DRAM_LA_START+MMU_SECTION_SIZE
	cmp	r3,r8		/* Done with first 1M? */
	beq	20f
	ldr	r7,=0x40000	/* Special check for 256K boundary */
	and	r7,r7,r5
	cmp	r7,#0
	beq	10b
	add	r5,r5,r7	/* Skip 256K hole */
	ldr	r7,=0x100000
	and	r7,r5,r7
	beq	10b
	add	r5,r5,r7	/* Nothing at 0xC0100000 */
	ldr	r7,=0x400000	/* Also nothing at 0xC0400000 */
	and	r7,r5,r7
	beq	10b
	add	r5,r5,r7
	b	10b
20:
/* 0x00100000..0x001FFFFF */
	mov	r6,r2		/* Set up page table descriptor */
	ldr	r7,=MMU_L1_TYPE_Page
	orr	r6,r6,r7
	str	r6,[r1],#4	/* Store PTE, update pointer */
10:	mov	r6,r5		/* Build page table entry */
	ldr	r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
	orr	r6,r6,r7
	ldr	r7,=MMU_PAGE_SIZE
	str	r6,[r2],#4	/* Next page */
	add	r3,r3,r7
	cmp	r3,r4		/* Done with first DRAM? */
	beq	20f
	add	r5,r5,r7
	ldr	r7,=0x40000	/* Special check for 256K boundary */
	and	r7,r7,r5
	cmp	r7,#0
	beq	10b
	add	r5,r5,r7	/* Skip 256K hole */
	ldr	r7,=0x100000
	and	r7,r5,r7
	beq	10b
	add	r5,r5,r7	/* Nothing at 0xC0300000 */
	ldr	r7,=0x400000	/* Also nothing at 0xC0400000 */
	and	r7,r5,r7
	beq	10b
	add	r5,r5,r7
	b	10b
20:

#elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
// The 16M EDB72xx boards are arranged as:
//   0xC0000000..0xC07FFFFF
//   0xC1000000..0xC17FFFFF
// The 16M EDB7312 board is arranged as:
//   0xC0000000..0xC0FFFFFF
        .macro  MAP_DRAM
/* Map DRAM */
	ldr	r3,=DRAM_LA_START
	ldr	r4,=DRAM_LA_END
	ldr	r5,=DRAM_PA
/* 0xXXX00000..0xXXXFFFFF */
10:	mov	r6,r2		/* Set up page table descriptor */
	ldr	r7,=MMU_L1_TYPE_Page
	orr	r6,r6,r7
	str	r6,[r1],#4	/* Store PTE, update pointer */
        ldr     r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE
#if !defined(__EDB7312)
// EDB7312 has contiguous SDRAM
	ldr	r9,=DRAM_PA_START+0x00800000   /* Skip at 8M boundary */
12:     cmp     r5,r9
        bne     15f
	ldr	r5,=DRAM_PA_START+0x01000000   /* Next chunk of DRAM */
#else
12:
#endif
15:	mov	r6,r5		/* Build page table entry */
	ldr	r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
	orr	r6,r6,r7
	ldr	r7,=MMU_PAGE_SIZE
	str	r6,[r2],#4	/* Next page */
	add	r3,r3,r7
	add	r5,r5,r7
        cmp     r3,r4           /* End of DRAM? */
        beq     20f
        sub     r8,r8,#1        /* End of 1M section? */
        cmp     r8,#0
        bne     12b             /* Next page */
        b       10b             /* Next section */
20:
        .endm
#else
#error Invalid DRAM size select
#endif

        .macro  MAP_L1_SEGMENT start end phys prot
	ldr	r3,=0x3FF	/* Page tables need 2K boundary */
	add	r2,r2,r3
	ldr	r3,=~0x3FF
	and	r2,r2,r3
	ldr	r3,=\start
	ldr	r4,=\end
	ldr	r5,=\phys
	ldr	r6,=\prot
	ldr	r7,=MMU_SECTION_SIZE
10:	orr	r0,r5,r6
	str	r0,[r1],#4
	add	r5,r5,r7
	add	r3,r3,r7
	cmp	r3,r4
	bne	10b
        .endm

        .macro  PLATFORM_SETUP1
        INIT_MEMORY_CONFIG
#ifdef CYG_HAL_STARTUP_RAM
        RELOCATE_RAM_IMAGE
#endif        
/* Initialize MMU to create new memory map */
	ldr	r1,=MMU_BASE
	ldr	r2,=PTE_BASE
	MAP_DRAM
/* Nothing until PCMCIA0 */
        MAP_L1_SEGMENT (DRAM_LA_END+0x000FFFFF)&0xFFF00000 EXPANSION2_LA_START 0 MMU_L1_TYPE_Fault
/* EXPANSION2, EXPANSION3, PCMCIA0, PCMCIA1 */
        MAP_L1_SEGMENT EXPANSION2_LA_START SRAM_LA_START EXPANSION2_PA MMU_L1_TYPE_Section|MMU_AP_Any
/* SRAM */
	ldr	r3,=SRAM_LA_START
	ldr	r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0)
	orr	r4,r4,r2
	str	r4,[r1],#4
	ldr	r7,=MMU_PAGE_SIZE
        ldr     r5,=SRAM_LA_END
05:	ldr	r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
	orr	r4,r3,r4
	str	r4,[r2],#4
        add     r3,r3,r7
        cmp     r3,r5
        bne     05b
	ldr	r4,=SRAM_LA_START+MMU_SECTION_SIZE
	ldr	r5,=MMU_L2_TYPE_Fault
10:	str	r5,[r2],#4
	add	r3,r3,r7
	cmp	r3,r4
	bne	10b
	ldr	r4,=IO_LA_START
	ldr	r5,=MMU_L1_TYPE_Fault
	ldr	r7,=MMU_SECTION_SIZE
20:	str	r5,[r1],#4
	add	r3,r3,r7
	cmp	r3,r4
	bne	20b
/* I/O */
	ldr	r3,=0x3FF	/* Page tables need 2K boundary */
	add	r2,r2,r3
	ldr	r3,=~0x3FF
	and	r2,r2,r3
	ldr	r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0)
	orr	r4,r4,r2
	str	r4,[r1],#4
	ldr	r3,=IO_LA_START
	ldr	r4,=IO_LA_END
	ldr	r7,=MMU_PAGE_SIZE
	ldr	r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All
10:	str	r5,[r2],#4
	add	r5,r5,r7
	add	r3,r3,r7
	cmp	r3,r4
	bne	10b
	ldr	r4,=IO_LA_START+MMU_SECTION_SIZE
	ldr	r5,=MMU_L2_TYPE_Fault
	ldr	r7,=MMU_PAGE_SIZE
10:	str	r5,[r2],#4
	add	r3,r3,r7
	cmp	r3,r4
	bne	10b
	ldr	r4,=LCD_LA_START
	ldr	r5,=MMU_L1_TYPE_Fault
	ldr	r7,=MMU_SECTION_SIZE
20:	str	r5,[r1],#4
	add	r3,r3,r7
	cmp	r3,r4
	bne	20b
/* LCD Buffer & Unmapped DRAM (holes and all) */
        MAP_L1_SEGMENT LCD_LA_START ROM0_LA_START LCD_PA MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
/* ROM0 */
        MAP_L1_SEGMENT ROM0_LA_START ROM0_LA_END ROM0_PA MMU_L1_TYPE_Section|MMU_AP_Any
/* ROM1 */
        MAP_L1_SEGMENT ROM1_LA_START ROM1_LA_END ROM1_PA MMU_L1_TYPE_Section|MMU_AP_Any
/* Now initialize the MMU to use this new page table */
	ldr	r1,=MMU_BASE
        MMU_INITIALIZE
#ifdef CYG_HAL_STARTUP_ROMRAM                                                  
        RELOCATE_TEXT_SEGMENT
#endif // CYG_HAL_STARTUP_ROM                                                          
        .endm
#endif // CYGSEM_HAL_STATIC_MMU_TABLES

#else  // CYGSEM_HAL_INSTALL_MMU_TABLES

#define PLATFORM_SETUP1
#endif
#endif //_CYGHWR_LAYOUT_ONLY

/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
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